Design Verification Engineer

Responsibilities Define and implement block/IP/SoC verification plans, build verification test benches to enable block/IP/sub-system/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the Design team Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality Minimum Qualifications Bachelor's degree in Electrical Engineering, Computer Science or other technically related fields 3+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog/UVM based methodologies Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle Preferred Qualifications Master’s degree in Electrical Engineering, Computer Science or other technically related fields. Experience in development of UVM based verification environments from scratch Experience with IP or integration verification of high-speed interfaces like PCIe, UCIe, DDR Experience with verification of ARM/RISC-V based sub-systems or SoCs Experience with Chisel is a plus Strong Python programming skills Good communication skills Contact [email protected]