Lead Analog / Mixed-Signal Layout Engineer

About TYLsemi, Inc. The Opportunity The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package? That's what we solve. TYLsemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale. This isn't a nice-to-have. It's the critical path. Why Now The Market Window The semiconductor industry is going through its biggest architectural shift in 40 years: • Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies. • Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually. • IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself. Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing. Culture & Team: How We Work No Politics, No Bureaucracy There are no layers, no approval chains, no corporate theater. • If you have an idea, we test it. If it works, we ship it. • No endless meetings, no PowerPoint presentations to convince middle management. Remote-Friendly, Global Team • US team: Bay Area preferred, but we hire the best people regardless of location • India team: Building a world-class design center in Bangalore Move Fast, Ship Real Products We're not a research project. We have paying customers, committed capital, and aggressive timelines. This is a company, not a lifestyle business. We're building to win. What We Value • Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it. • Bias for action. We move fast. Analysis paralysis doesn't fly here. • Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware. • Low ego, high standards. We don't care about titles or politics. We care about results. The Ask If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits. We're asking you to walk away from that and bet on us. Here's why you should: • The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building. • The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo. • The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue. • The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI. This is the bet. Join us and build something that matters. Or stay comfortable. No judgment. But if you're the kind of person who wants to take the shot, we'd love to talk. READY TO JOIN? About the Role TYLsemi is seeking an experienced Analog / Mixed-Signal Layout Lead to drive physical design execution for analog and mixed-signal IP blocks on advanced FinFET process nodes. This role owns layout strategy, integration, and sign-off for high-performance power and analog circuits, and serves as the primary technical interface with external layout/design-service partners and foundry teams. What You’ll Do Lead layout planning, floorplanning, and execution for analog and mixed-signal blocks (e.g., power converters, IVRs, references, amplifiers, ADC/DAC front-ends) on FinFET-based advanced nodes. Define and enforce analog layout techniques: matching, symmetry, common-centroid structures, guard-ringing, shielding, and parasitic-aware placement/routing for sensitive analog nets. Own integration guidelines between analog/mixed-signal blocks and digital logic, ensuring clean floorplan partitioning, power delivery, and signal integrity across the top-level chip. Identify and resolve advanced-node layout issues — including multi-patterning (MP) constraints, color-aware routing, restrictive design rules (RDRs), via pillars, local interconnect limitations, and device-level layout-dependent effects (LDE, well-proximity, STI stress). Drive DRC/LVS/PERC/antenna closure and coordinate ECO layout cycles with design and verification teams. Manage layout schedules, milestones, and quality across internal teams and external layout vendors/subcontractors, including scope definition, kickoff, technical reviews, and issue resolution. Interface with packaging teams for integration on advanced packaging (2.5D/3D, microbump, RDL) layout requirements. Define and drive layout methodology strategy, including use of APR (Automatic Place & Route) tools for applicable analog-assisted and mixed-signal blocks, custom scripting/automation (e.g., SKILL, Python) to speed up placement, routing, and DRC/LVS cleanup, and PCells/parameterized layout generation to improve reuse and reduce turnaround time. Mentor junior layout engineers and establish reusable layout methodologies, checklists, and best-practice documentation. What We’re Looking For Bachelor's or Master's degree in Electrical Engineering, Microelectronics, or related field. 10+ years of layout experience in the semiconductor industry, with significant time on FinFET process nodes (16nm and below). 2+ years of leadership experience, such as leading a layout team, mentoring engineers, or owning layout schedules/deliverables across a project. Strong hands-on expertise in analog/mixed-signal layout techniques for power management, reference, or precision analog circuits. Deep familiarity with advanced-node layout constraints: multi-patterning, restricted design rules, device orientation/matching rules, and layout-dependent effects. Proven experience defining or applying analog-digital integration guidelines at the block and top level. Familiarity with layout automation and APR methodologies, and their applicability/limitations for analog and mixed-signal design. Track record of managing or closely collaborating with external layout teams, design service providers, or offshore layout groups. Proficiency with industry-standard layout/verification tools (e.g., Cadence Virtuoso, Calibre DRC/LVS/PERC). Solid understanding of parasitic extraction, IR drop, EM/reliability considerations for power-carrying layout.