Senior Engineer – LEC / CLP (Logical Equivalence & Low Power Convergence)

About TYLsemi, Inc. The Opportunity The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package? That's what we solve. TYLsemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale. This isn't a nice-to-have. It's the critical path. Why Now The Market Window The semiconductor industry is going through its biggest architectural shift in 40 years: • Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies. • Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually. • IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself. Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing. Culture & Team: How We Work No Politics, No Bureaucracy There are no layers, no approval chains, no corporate theater. • If you have an idea, we test it. If it works, we ship it. • No endless meetings, no PowerPoint presentations to convince middle management. Remote-Friendly, Global Team • US team: Bay Area preferred, but we hire the best people regardless of location • India team: Building a world-class design center in Bangalore Move Fast, Ship Real Products We're not a research project. We have paying customers, committed capital, and aggressive timelines. This is a company, not a lifestyle business. We're building to win. What We Value • Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it. • Bias for action. We move fast. Analysis paralysis doesn't fly here. • Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware. • Low ego, high standards. We don't care about titles or politics. We care about results. The Ask If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits. We're asking you to walk away from that and bet on us. Here's why you should: • The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building. • The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo. • The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue. • The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI. This is the bet. Join us and build something that matters. Or stay comfortable. No judgment. But if you're the kind of person who wants to take the shot, we'd love to talk. READY TO JOIN? Role Overview As a Senior Engineer in LEC/CLP , you will play a key role in ensuring functional correctness and low-power intent integrity across the design lifecycle. You will be responsible for equivalence checking as well as validating UPF/CPF-based low-power implementations, ensuring seamless convergence between RTL, synthesis, and physical design stages for successful tape-out. What You’ll Do Perform RTL-to-Gate and Gate-to-Gate equivalence checks using tools like Cadence Conformal or Synopsys Formality Validate low-power design intent (UPF/CPF) and ensure correctness of power-aware transformations Debug LEC failures, including issues arising from clock gating, retention, isolation, and level shifters Ensure convergence of LEC and CLP across synthesis, place-and-route, and ECO cycles Work closely with RTL, Synthesis, DFT, and Physical Design teams to resolve design mismatches Handle ECO validation and ensure equivalence closure post-design changes Develop automation scripts and improve methodology for LEC/CLP sign-off What We’re Looking For Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related discipline 5+ years of experience in Formal Verification, LEC, and Low Power Verification Strong expertise in tools like Cadence Conformal LEC/LP or Synopsys Formality/VC LP Solid understanding of low-power design concepts (UPF/CPF), clock gating, power domains Experience with synthesis, netlist optimizations, and equivalence debugging Proficiency in scripting languages such as TCL, Python, or Perl Good to Have Exposure to advanced low-power techniques (multi-Vt, DVFS, power gating) Experience with hierarchical SoC-level LEC/CLP flows Familiarity with DFT concepts and scan impact on equivalence Knowledge of STA and Physical Design interactions impacting LEC/CLP Success in This Role Looks Like Clean LEC/CLP sign-off with zero functional or power-intent mismatches Fast turnaround time in debugging and resolving equivalence issues Robust, scalable LEC/CLP methodologies across projects Strong cross-team collaboration ensuring smooth design convergence Location Hybrid / On-site – Bengaluru