Senior Physical Design Engineer

About TylSemi, Inc. The Opportunity The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package? That's what we solve. TylSemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale. This isn't a nice-to-have. It's the critical path. Why Now The Market Window The semiconductor industry is going through its biggest architectural shift in 40 years: • Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies. • Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually. • IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself. Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing. Culture & Team: How We Work No Politics, No Bureaucracy There are no layers, no approval chains, no corporate theater. • If you have an idea, we test it. If it works, we ship it. • No endless meetings, no PowerPoint presentations to convince middle management. Remote-Friendly, Global Team • US team: Bay Area preferred, but we hire the best people regardless of location • India team: Building a world-class design center in Bangalore Move Fast, Ship Real Products We're not a research project. We have paying customers, committed capital, and aggressive timelines. This is a company, not a lifestyle business. We're building to win. What We Value • Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it. • Bias for action. We move fast. Analysis paralysis doesn't fly here. • Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware. • Low ego, high standards. We don't care about titles or politics. We care about results. The Ask If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits. We're asking you to walk away from that and bet on us. Here's why you should: • The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building. • The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo. • The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue. • The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI. This is the bet. Join us and build something that matters. Or stay comfortable. No judgment. But if you're the kind of person who wants to take the shot, we'd love to talk. READY TO JOIN? Role Overview We are looking for a Senior Physical Design Engineer to own and drive the implementation of complex digital SoCs from synthesis through tapeout. You will work at the intersection of design and process, translating RTL into silicon-ready layouts that meet aggressive PPA targets. This role exists to ensure our chips are not only functionally correct but physically optimized, manufacturable, and delivered on schedule. What You'll Do Lead floorplanning, placement, CTS, routing, and signoff for one or more design blocks or full-chip subsystems Drive timing closure across multiple corners and modes using industry-standard EDA tools (Cadence Innovus, Synopsys ICC2, or equivalent) Perform and interpret IR drop, EM, DRC, LVS, and antenna analyses; own resolution of violations Collaborate with RTL designers, DFT, and verification teams to ensure physical constraints align with design intent Work with foundry and PDK teams to validate design rules and address process-specific requirements Contribute to methodology improvements — scripts, flows, and automation to improve turnaround time and quality of results Mentor junior engineers and review their work at key implementation milestones What We're Looking For 5+ years of hands-on physical design experience on advanced-node designs (16nm or below preferred) Deep expertise in the full PD flow: floorplanning → placement → CTS → routing → signoff Strong understanding of timing analysis, STA constraints (SDC), and multi-corner multi-mode (MCMM) closure Proficiency with at least one major implementation tool suite (Cadence or Synopsys) and signoff tools (Tempus, PrimeTime, Voltus, RedHawk) Solid grasp of low-power design techniques — power gating, multi-voltage domains, UPF/CPF Experience working directly with foundry PDKs (TSMC, Samsung, or equivalent) through tapeout Good to Have Exposure to custom or mixed-signal blocks and interface IP integration (PCIe, DDR, USB) Scripting proficiency in Tcl, Python, or Perl for flow automation Prior experience in a tapeout lead or block owner role on a production chip Success in This Role Looks Like Blocks are delivered to signoff with PPA targets met — timing clean, no DRC/LVS violations, power within budget Tapeout milestones are hit on schedule with minimal late-stage surprises or re-spins attributable to physical implementation Flow and methodology improvements you drive measurably reduce runtime or improve QoR for the broader team Junior engineers grow faster and make fewer critical mistakes because of your technical guidance and code/design reviews