Sr Staff Engineer, Design Verification

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Responsibilities Coding of simulation infrastructure using SystemVerilog (UVM) & C/(ARM,RISC-V Assembly) SoC Level verification is a must. Actively involve in all stages of product development including specification, circuit design, circuit modeling, verification, design for test, and silicon debug. Set up UVM verification environment, develop, and verify self-tested test benches for Mixed Signal chips and sub-circuits. Use and Development of Advanced UVM/mixed-signal simulation techniques to enhance simulation efficiency. Generate Verification Plan from the Specifications using vManager Determine Coverage and design completeness requirements Generate random-constraint tests to cover all customer-use-models Create Assertions, cover-groups, checkers, monitors and automatic reporting Set-up and run regression reports Works diligently to accomplish project goals and meet schedule requirements Job Requirements BSEE (MSEE pref.) or equivalent with 10+ years professional industry experience in Digital multi core SoC verification. Experience in digital Verification. Mixed-signal Verification is plus. UVM testbench creation, writing and implementation is a plus. Proficient developing scripts (Shell, Perl, Python etc.), and Cadence SKILL language is plus Experience with RN(Real Number)/Digital top-level modeling and verification methodology to speed up simulation (understanding accuracy/speed tradeoff and interfaces) Must be able to work independently with limited supervision and work closely with team. Work from office. Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement .