Computer Aided Design Engineer

EDA/CAD Engineer — AI-Powered Physical Chip Design | $6M Raised | Los Altos, CA

Solve the problems humans literally can't solve alone

Our new client is an AI-powered EDA startup rewriting how semiconductor chips get physically designed. As Moore's Law runs out of road and compute demand keeps exploding, most AI EDA players are just automating what engineers already do. This team is different — they're using AI to push past what humans can achieve manually, weaving downstream manufacturing data from fabs like TSMC and GlobalFoundries directly into the upstream design process to find PPA (power, performance, area) breakthroughs that traditional methodologies leave on the table.

They're the only startup tackling AI-driven PPA optimization in physical design — and they're already proving it out with major semiconductor companies, including a publicly announced partnership with GlobalFoundries.

Why join now

• Ground floor, real traction. $6M pre-seed closed, next round closing soon. 5 people today, hiring 3–7 engineers — you'd be employee #6-12, not #600.
• World-class founding team. A former Google exec who led 300- and 600-person teams (Search app, Assistant), plus 7 years at Intel building their first power estimation tool — paired with an endowed EE chair and one of the most decorated names in EDA/VLSI CAD research (500+ papers, a record 20 best-paper awards). Advised by the last person to take an EDA company public.
• No bureaucracy. Engineers own significant pieces of the product and present directly to customers, weekly.
• Culture built on transparency and ownership — not hours logged. High-bandwidth, on-site collaboration Monday–Thursday, WFH Fridays.
• The office itself: a 5-minute walk to downtown Los Altos, daily free lunch, stocked micro kitchen.
• Compensation: They are willing to pay above market for top talent plus visa sponsorship and relocation bonus for strong candidates.

What you'll actually do

• Implement complex design rules from major foundries into an AI-powered physical design optimization system
• Build EDA software focused on place & route, PPA optimization, and backend IC implementation — not just run existing tools
• Work directly with top-tier semiconductor customers on a weekly basis, owning customer-facing deliverables
• Split your time between tactical wins (closing gaps, shipping features, fixing bugs) and strategic bets (agentic flows, pre-trained model integration)
• Work shoulder-to-shoulder with a small, elite team of PhDs and engineers

Who we're looking for

• 2–8 years in VLSI physical design or EDA tool development
• Hands-on place & route or physical design R&D experience
• A track record of building EDA tools, not just scripting around them
• Background at Synopsys, Cadence, Intel, Nvidia, or a similar bar
• BS/MS/PhD in EE, Computer Engineering, or CS from a strong program
• Comfortable with advanced process nodes (7nm and below)
• Algorithmic/optimization mindset — you want to build the tools, not just drive them
• Tech stack exposure: Cadence, Synopsys, Python, Tcl, Perl, DRC

Not a fit if: you've spent 20+ years at one large company, your experience is purely frontend/RTL with no backend exposure, or you're a script-runner without interest in algorithms and optimization.

Location: On-site 4 days/week (Mon–Thu) in Los Altos, CA. WFH optional Fridays.

The best engineers don't wait for the rules to change — they rewrite them. If that's you we would love to hear from you! 👻