Expert PLL Design Engineer

We are seeking a highly skilled and experienced Expert PLL Design Engineer to join our team. This role is pivotal in the architecture, design, and silicon validation of ultra-low-jitter phase-locked loops (PLLs) and frequency synthesizers. The successful candidate will take ownership of PLL performance from concept through production release, ensuring high-quality, spec-compliant designs. If you are passionate about cutting-edge technology and thrive in a collaborative, fast-paced environment, we encourage you to apply. Applications from all over the world are welcome and will be considered depending on suitability. Visa can be provided. The opportunity is office based in The Netherlands or Germany.

Responsibilities

• Define and develop ultra-low-jitter PLL and fractional-N frequency synthesizer architectures for precision timing products.
• Architect and design high-performance PLLs
• Design and simulate critical PLL sub-blocks, including VCOs/DCOs, charge pumps, phase-frequency detectors, loop filters, dividers, delta-sigma modulators, and time-to-digital converters (TDCs).
• Perform phase-noise and jitter budgeting across the loop to achieve sub-50 fs integrated jitter.
• Write detailed block-level PLL specifications and behavioral/system models (e.g., Verilog-A, MATLAB).
• Drive electromagnetic (EM) simulations of critical passives and interconnects to optimise layout and floor-planning.
• Collaborate with cross-functional teams to integrate PLL designs, achieve rapid silicon bring-up, and enable fast production release.
• Supervise and mentor junior and senior analog circuit designers.

Qualifications

• MS in Electrical Engineering required; PhD preferred.
• 8+ years of experience in high-performance analog/mixed-signal circuit design, with a primary focus on PLLs and frequency synthesizers.
• Proven track record of designing ultra-low-jitter, power-efficient fractional-N PLLs achieving.
• Hands-on experience with advanced PLL architectures such as sampling PLLs, sub-sampling PLLs, and multi-phase PLLs.
• Expertise in PLL architecture development, modeling, design, and budgeting for phase-noise, jitter, and power.
• Experience with lab characterization of PLLs using phase-noise analyzers, spectrum analyzers, and jitter measurement tools.
• Excellent written and verbal communication skills.
• Proven experience leading/supervising

Compensation package

• Competitive compensation package including shares.
• Comprehensive health, dental, and vision insurance.
• Generous paid time off and holiday schedule.
• Opportunities for professional growth and development.
• Collaborative and innovative work environment.
• Access to state-of-the-art tools and technologies.

Please contact Ane @ IC Resources with your CV and a time for an initial call if you want to know more about this role. I will send you the full job description prior to our conversation!