Member of Technical Staff, Hardware, Performance Engineer

At River, our mission is to create personal AI owned and shaped by each individual. To achieve this, we are rewriting the entire stack from scratch: personal hardware for local inference, custom training infrastructure, next-generation UIs, and frontier deep learning research. Who we are We are scientists, engineers, and builders from the industry's top tech companies and AI labs. We bring a proven track record of scaling consumer systems for hundreds of millions of users and architecting the pre-training infrastructure behind today's frontier models. About the Role We are looking for exceptional performance engineers to architect, model, and correlate high-performance custom silicon. You will develop high-fidelity simulators to predict how our AI accelerator architecture and SoC system will handle real-world AI models. You will take ownership of performance models, ISA and kernel optimization, and FPGA emulators for software development. You will be collaborating both up and down the stack with compiler, IR, and software teams, as well as with RTL design engineers. What You’ll Do Simulator Development: Design and implement high-performance and functional models of complex hardware using C++ and/or SystemC. Micro-architectural Exploration: Conduct "what-if" studies to evaluate architectural changes (e.g., cache sizes, branch predictors, pipeline depths, scatter/gather, matmul shaping) and their impact on IPC, MFU, TTFT, and total execution time. Workload Characterization: Analyze and profile AI kernels and software stacks to generate representative traces that stress-test the hardware models. HW/SW Co-Design: Collaborate with compiler and kernel teams to optimize software mapping to hardware, ensuring the architecture supports emerging algorithmic breakthroughs efficiently. Performance Correlation: Validate the performance model against RTL and pre-silicon emulators to ensure the model’s accuracy remains within strict tolerance levels. Bottleneck Analysis: Identify and quantify system-level bottlenecks, ranging from instruction-level parallelism (ILP) limits to bandwidth throttling to utilization. Skills and Qualifications Minimum Qualifications: Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical industry experience working with advanced process nodes (7nm or below). Expert proficiency in C/C++ or event-driven simulation environments like SystemC Hands-on experience with how compilers transform code (LLVM/GCC/XLA) and how high-performance kernels (CUDA/Triton) interact with the underlying ISA. Expert knowledge in Computer Architecture of at least one style of chip, including SoCs, CPUs, GPUs, or AI accelerators Experience with profiling hardware with performance counters, hardware profilers, and trace analysis tools to dissect application behavior. A highly collaborative mindset to push boundaries and co-design effectively with other engineers. Preferred Qualifications: (We encourage you to apply even if you don't meet all of these) Hands-on experience in pre-silicon RTL/emulator and/or post-silicon performance validation Knowledge or experience of QEMU models for pre-silicon software development Proficiency in scripting for data post-processing, visualization of simulation results, and automation of massive regression suites. Logistics Location: This role is based in Austin, Texas or Palo Alto, California. Compensation: Depending on background, skills, and experience, the expected annual salary range for this position is $200,000 - $420,000 USD. Visa Sponsorship: We sponsor visas. We can't guarantee success for every candidate or role, but if you're the right fit, we're committed to working through the visa process. Benefits: River AI offers generous health, dental, and vision benefits, unlimited PTO, and relocation support as needed.