Senior Validation Engineer – DDR Subsystems

Based in Hampshire, our client is looking for a Validation Engineer with a strong understanding of DDR protocols, FPGA development and system bring-up to join their leading satellite communications team.

In this role the Senior Validation Engineer will be responsible for validating DDR3/DDR4 interfaces on modem platforms. FPGA development and prototyping will also be a key part of the role, as will performing board bring-up and system integration, and Python / C++ programming for automation. The Validation Engineer will be working closely with digital RTL design, PHY design, PCB and software teams, and build a broad, in-depth understanding of the end-to-end system.

Requirements Include

• Bachelor’s or Master’s degree in Electrical Engineering or similar field
• A number of years of experience in DDR validation, FPGA development, or high-speed digital systems
• Excellent experience with validation equipment, such as oscilloscopes, JTAG debuggers, etc
• Strong understanding of DDR architecture and JEDEC standards, and high-speed interfaces
• Excellent communication and documentation abilities
• Hands-on skills in Python / C++ programming
  
  

On top of a competitive basic salary, you’ll receive a benefits package including private healthcare, life insurance, pension plan, and visa sponsorship if needed.

Get in touch for details: please contact Caroline Pye.