Analog IC Design Engineer - Core Analog Blocks (Junior / Mid-level)

About Caravel

Caravel Semiconductor is a Portuguese analog and mixed-signal IC design house. We design analog IP — PLLs and oscillators, regulators and references, RF front-ends, data converters and ESD — for clients in the semiconductor space.

The role

We're looking for an analog IC designer to focus on the building blocks every chip depends on: LDOs, bandgap references, comparators, bias networks and amplifiers. You'll own these blocks end to end — spec, schematic, simulation, layout supervision and silicon bring-up — with senior designers alongside you.

What you'll do

• Design LDOs (with and without external capacitor), bandgap and current references, comparators, op-amps and OTAs, bias networks and power-management blocks from specification to tape-out

• Simulate across PVT corners and Monte Carlo: stability, PSRR, noise, offset, line and load transients, start-up

• Drive layout with matching, symmetry and parasitic-aware floorplanning; close the post-layout loop

• Integrate your blocks at top level: power domains, ESD, verification together with the digital and RF teams

• Document your work, take part in design reviews, and support silicon evaluation and correlation with simulation

What we're looking for

• MSc (or equivalent) in Electrical Engineering, Microelectronics or a related field

• 1–5 years of hands-on analog IC design experience (thesis work and internships count for junior candidates)

• Solid transistor-level fundamentals: feedback and stability, noise, mismatch and offset, PVT variation

• Working knowledge of a full-custom analog design flow — schematic capture, SPICE-class simulation, layout — in Cadence, Synopsys or an equivalent environment

• Proactive, detail-oriented, and committed to high standards of reliability and performance

• Collaborative team player

• Good written and spoken English

• Based in, or willing to relocate to, the Porto area

Nice to have

• A taped-out LDO, reference or comparator you can talk about, in a product or a thesis

• Familiarity with the Synopsys custom design flow (Custom Compiler, PrimeSim / HSPICE) alongside the Cadence one (Virtuoso, Spectre)

• Comfortable working in a Linux environment (shell, remote compute, batch simulation runs)

• Scripting for automation (Python, SKILL, Ocean, TCL)

What we offer

• Hybrid work: 2-3 days a week at the Porto office, the rest remote

• Design responsibility from day one, with mentoring from senior engineers

• A small team where your work goes to silicon, with no layers between you and the tape-out

• Engage in exciting national and international projects

• Health insurance

How to apply

• Send your CV and a short note on what you've designed (thesis, projects, tape-outs) to careers@caravelsemi.com