Application Specific Integrated Circuit Design Engineer

🚀 ASIC Design Engineer | £175K–£200K | OUTSIDE IR35 OR High Pay Permanent

📍 UK | Hybrid – up to 3 days onsite in Oxford, 2 days remote

I’m partnering with an innovative technology business working at the forefront of AI based quantum computing is seeking an experienced ASIC Design Engineer to take end-to-end ownership of a next-generation processor architecture.

This is a rare opportunity to lead the miniaturisation of a cutting-edge computing platform, shaping everything from algorithms and instruction set architecture (ISA) through to microarchitecture, tape-out and silicon bring-up.

🔧 The Role

You’ll take ownership of the ASIC architecture, translating complex workloads into an optimised hardware platform while driving critical architectural decisions across performance, power and area.

Key responsibilities include:

• System Architecture & ISA: Define system-level architecture, instruction sets and dataflow models based on workload requirements.
• Performance Modelling: Develop functional simulations and hands-on performance models using Python, C++ or equivalent to drive architectural decisions.
• Hardware/Software Co-Design: Analyse arithmetic implementation, programmability, fixed-function hardware and host-system requirements.
• Microarchitecture: Define detailed specifications covering RTL requirements, memory hierarchy, on-chip and inter-chip connectivity, and hardware/software interfaces.
• PPA Optimisation: Lead architectural partitioning and trade-off analysis across timing, power and area, with physical design awareness.
• IP & Integration: Oversee internal IP development and evaluate third-party IP.
• Silicon Delivery: Guide the design through verification strategy, sign-off, tape-out and bring-up.

🧠 What We're Looking For

• Proven architectural ownership of at least one ASIC through successful tape-out.
• Experience with compute accelerators, inference engines, DSPs or comparable processor architectures.
• Strong hands-on performance modelling and simulation skills using Python, C++ or equivalent.
• Experience with industry-standard EDA tools and flows, such as Synopsys, Cadence or Siemens.
• A solid understanding of architectural trade-offs involving timing, power and area.
• Experience defining hardware/software interfaces and working with firmware and compiler teams.
• Strong RTL design experience and the ability to define verification strategies at architectural level.

💰 Package & Working Arrangement

✅ £175,000–£200,000

✅ Outside IR35 contract or permanent employment (Permanent is preferable given the longevity of the work but if the suitable applicant is interested in contract initially it is still worth applying).

✅ Hybrid working: up to 3 days onsite and 2 days remote per week

✅ Industry Leading benefits (Available on request)

✅ Significant architectural ownership from system-level design through to silicon

Why consider it?

This is an opportunity to shape the architecture of an ambitious, next-generation probabilistic computing processor, influence fundamental design decisions and take ownership of a technology platform from initial modelling through to physical silicon.

If you’re an ASIC Architect who enjoys solving complex engineering challenges and wants to make a tangible impact on next-generation computing, I’d welcome a confidential conversation.

📩 Interested? Please apply with an up to date CV, alternatively Send me a message, or get in touch if you know someone who would be a strong fit.

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