Co-Founder & CTO — AI Accelerator / ASIC Architecture
NeuraSiliconCo-Founder & CTO — AI Accelerator / ASIC Architecture
NeuraSilicon | Remote | International / Worldwide
ABOUT NEURASILICON
NeuraSilicon is an early-stage semiconductor startup building NS A400 — an AI-native accelerator platform focused on next-generation AI compute, agentic workloads, and hardware/software co-design.
We are building a vertically integrated compute stack spanning:
NS A400 Architecture
→ NeuraCore
→ Memory Architecture
→ Neura ISA
→ NeuraCompiler
→ AI Execution Framework
→ RTL
→ FPGA Validation
→ ASIC Development
We are now looking for an exceptional international technical co-founder to join NeuraSilicon as:
CO-FOUNDER & CTO — AI ACCELERATOR / ASIC ARCHITECTURE
This is a hands-on founding role.
We are NOT looking for someone who only wants a CTO title.
We are looking for a builder who wants to help design a new AI compute architecture from the ground up.
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WHAT YOU WILL OWN
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You will have major technical ownership of NS A400 hardware development.
Responsibilities may include:
• NS A400 microarchitecture
• NeuraCore architecture
• RTL development using Verilog/SystemVerilog
• Processing-element design
• Pipelines and control logic
• Memory hierarchy
• SRAM interfaces
• DMA and data movement
• Cache architecture
• Interconnect / NoC
• RTL verification
• FPGA prototyping
• Synthesis
• Performance modeling
• Hardware/software co-design
• Neura ISA hardware interfaces
• NeuraCompiler integration
• ASIC architecture roadmap
• Future silicon engineering team leadership
You will work directly on the technical architecture — not only manage engineers.
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IDEAL TECHNICAL BACKGROUND
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Strong experience or demonstrated ability in several of:
• Verilog / SystemVerilog
• RTL design
• FPGA development
• ASIC / VLSI design
• Computer architecture
• GPU / NPU / AI accelerator architecture
• Digital logic
• Pipeline architecture
• Memory systems
• SRAM / cache hierarchy
• RTL verification
• Synthesis
• Timing concepts
• Performance modeling
Strong bonus experience:
• RISC-V
• AXI
• NoC
• PCIe
• DMA
• SIMD / vector architectures
• Tensor / matrix accelerators
• CUDA / GPU architecture
• LLVM / MLIR
• Vivado
• Quartus
• Verilator
• Yosys
• OpenROAD
• RTL-to-GDSII flows
You do NOT need experience with every technology listed.
We care much more about engineering ability and what you have actually built.
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WHO SHOULD APPLY
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Strong candidates may come from:
• Semiconductor companies
• CPU / GPU teams
• AI accelerator startups
• FPGA engineering
• ASIC / VLSI engineering
• RISC-V development
• Computer architecture research
• University research laboratories
• Open-source silicon projects
• Compiler / architecture research
Exceptional graduate students, researchers, independent engineers and open-source contributors are also welcome.
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WHAT WE VALUE
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We are looking for someone who:
• Loves building difficult systems
• Can write and review RTL
• Thinks deeply about compute and memory architecture
• Challenges technical assumptions
• Can prototype quickly
• Understands performance bottlenecks
• Wants long-term technical ownership
• Is comfortable working across hardware and software
• Wants to build a semiconductor company, not simply join one
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CURRENT NS A400 DEVELOPMENT
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Our current development sequence includes:
Memory Simulator
→ Balanced NeuraCore
→ Neura ISA
→ NeuraCompiler
→ AI Execution Framework
→ RTL
→ FPGA Prototype
→ ASIC Path
The architecture is early enough that the selected co-founder can meaningfully influence fundamental design decisions.
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NEAR-TERM TECHNICAL GOAL
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We are working toward an end-to-end NS A400 prototype demonstrating:
AI Workload
→ NeuraCompiler
→ Neura ISA
→ NeuraCore
→ Memory System
→ Performance Analysis
→ RTL
→ FPGA Validation
Key metrics will eventually include:
• Compute utilization
• Memory bandwidth
• Latency
• Throughput
• Scaling
• Power / energy modeling
• Hardware efficiency
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FOUNDER OPPORTUNITY
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IMPORTANT:
This is an early-stage CO-FOUNDER opportunity.
This role is currently unpaid.
It is not a conventional salaried CTO position.
The selected co-founder will receive meaningful founder equity with vesting terms to be mutually agreed upon.
The intention is to transition the founding team toward full-time compensated roles as financing permits.
NeuraSilicon is preparing for the Y Combinator Winter 2027 application cycle.
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LOCATION
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Remote / International.
We are actively looking for exceptional candidates from:
• United States
• Canada
• United Kingdom
• Germany
• France
• Netherlands
• Switzerland
• Sweden
• Finland
• UAE
• Singapore
• Taiwan
• South Korea
• Japan
• Australia
• India
• Other global semiconductor and AI engineering ecosystems
Strong candidates worldwide are welcome.
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HOW TO APPLY
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Please send your application to:
asadshar0123@gmail.com
Include:
1. GitHub / portfolio / publications
2. Your strongest RTL, FPGA, ASIC, CPU, GPU or accelerator project
3. Your strongest technical area
4. Current country and time zone
5. Current availability
6. Approximate weekly commitment
7. Whether you could transition to full-time if NeuraSilicon receives funding
8. Why you want to build an AI semiconductor startup
9. Which part of NS A400 you would most like to own
10. One thing you believe current GPU / AI accelerator architectures should fundamentally improve
Email subject:
NeuraSilicon CTO Co-Founder Application — [Your Name]
NEURASILICON
Building the next generation of AI compute —
from architecture and compiler to silicon.