Ethernet Scale-Up Design Lead/Principal Engineer

About TYLsemi, Inc. The Opportunity The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package? That's what we solve. TYLsemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale. This isn't a nice-to-have. It's the critical path. Why Now The Market Window The semiconductor industry is going through its biggest architectural shift in 40 years: Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies. Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually. IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself. Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing. Culture & Team: How We Work No Politics, No Bureaucracy There are no layers, no approval chains, no corporate theater. If you have an idea, we test it. If it works, we ship it. No endless meetings, no PowerPoint presentations to convince middle management. Remote-Friendly, Global Team US team: Bay Area preferred, but we hire the best people regardless of location India team: Building a world-class design center in Bangalore Move Fast, Ship Real Products We're not a research project. We have paying customers, committed capital, and aggressive timelines. This is a company, not a lifestyle business. We're building to win. What We Value Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it. Bias for action. We move fast. Analysis paralysis doesn't fly here. Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware. Low ego, high standards. We don't care about titles or politics. We care about results. The Ask If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits. We're asking you to walk away from that and bet on us. Here's why you should: The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building. The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo. The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue. The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI. This is the bet. Join us and build something that matters. Or stay comfortable. No judgment. But if you're the kind of person who wants to take the shot, we'd love to talk. READY TO JOIN? About the role TYLsemi is developing purpose-built connectivity chiplet for HPC/rack-scale AI systems. We are seeking a Principal Engineer Ethernet Scale-up to lead the architecture and design of next-generation Ethernet Scale-Up Networking (ESUN) solution. This is a high-impact technical role. What You'll Do Define architecture for Ethernet-based AI scale-up interconnects and accelerator fabrics. Lead development of high-performance Ethernet Subsystem microarchitectures including RDMA, packet processing, network offload, traffic management, congestion control, and reliability mechanisms. Drive execution from architecture through RTL, verification, physical design, silicon bring-up, and production. Optimize performance, latency, scalability, power, and reliability for demanding AI and HPC workloads. Collaborate across hardware, firmware, software, and system teams to deliver industry-leading AI networking solutions. Serve as a company-wide technical leader, influencing product strategy, roadmap, and architectural direction. Qualifications 15+ years of ASIC/SoC architecture and design experience. Proven track record delivering networking, NIC, switch, DPU, accelerator interconnect, or high-speed connectivity silicon. Deep expertise in SystemVerilog/RTL design and high-performance datapath architecture. Strong knowledge of Ethernet, RDMA, traffic management, congestion control, and scalable fabric architectures. Experience across the full ASIC lifecycle, from architecture to production silicon. Preferred Experience Ultra Ethernet, UALink, RoCEv2, InfiniBand PCIe Gen6/Gen7, UCIe, CXL AI/HPC interconnects and collective communication acceleration 400G/800G/1.6T Ethernet systems High-speed SerDes and advanced networking architectures Why Join Us? Define the future of AI infrastructure and rack-scale computing. Own architecture decisions with company-wide impact. Deliver technology that directly impacts AI performance, scalability, and efficiency.