FPGA Engineer – High-Speed Digital Design
- Hiring from
- Switzerland
- Work type
- Hybrid
- Posted
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Assignment: 80%
Duration: 3 months
Start date: ASAP
Location: Remote, with an initial hybrid period in Lausanne
About the assignment
Our client is a leading technology company developing high-speed connectivity solutions and digital IP. As part of its engineering team, you will support FPGA prototyping, device validation, and the bring-up of high-speed digital designs for PHY and SerDes IP.
Key responsibilities
Support FPGA prototyping for high-speed digital designs related to PHY and SerDes IP.
Contribute to the validation and bring-up of devices and FPGAs in the laboratory.
Work closely with Firmware, Digital Design, Verification, and Lab teams.
Support design validation, testing, and troubleshooting activities.
Contribute to the setup and improvement of development and validation environments.
Required skills and experience
At least 10 years of experience in FPGA design and prototyping.
Strong experience designing and prototyping FPGA blocks for multi-Gigabit serial and parallel data-link transceivers.
Excellent RTL coding skills, preferably in SystemVerilog.
Experience with industry-standard FPGA tools for design, simulation, and verification.
Experience with Python or another scripting language for design validation and tool setup.
Strong technical background in FPGA design, validation, and verification.
Experience with high-speed digital blocks; knowledge of high-speed interfaces and/or PCS is an advantage.
Good understanding of verification methodologies; experience with UVM is a plus.
Strong analytical, communication, and teamwork skills.
Working model
The first two weeks will follow a hybrid model, with three days per week on-site in Lausanne and two days remote. The assignment can then be performed fully remotely, although a hybrid setup remains preferred throughout the three-month assignment.