Senior RTL Designer - Interconnect/NoC Design

About TylSemi, Inc. The Opportunity The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package? That's what we solve. TylSemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale. This isn't a nice-to-have. It's the critical path. Why Now The Market Window The semiconductor industry is going through its biggest architectural shift in 40 years: • Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies. • Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually. • IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself. Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing. Culture & Team: How We Work No Politics, No Bureaucracy There are no layers, no approval chains, no corporate theater. • If you have an idea, we test it. If it works, we ship it. • No endless meetings, no PowerPoint presentations to convince middle management. Remote-Friendly, Global Team • US team: Bay Area preferred, but we hire the best people regardless of location • India team: Building a world-class design center in Bangalore Move Fast, Ship Real Products We're not a research project. We have paying customers, committed capital, and aggressive timelines. This is a company, not a lifestyle business. We're building to win. What We Value • Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it. • Bias for action. We move fast. Analysis paralysis doesn't fly here. • Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware. • Low ego, high standards. We don't care about titles or politics. We care about results. The Ask If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits. We're asking you to walk away from that and bet on us. Here's why you should: • The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building. • The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo. • The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue. • The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI. This is the bet. Join us and build something that matters. Or stay comfortable. No judgment. But if you're the kind of person who wants to take the shot, we'd love to talk. READY TO JOIN? We are looking for System On-chip/SoC Fabric micro-architect and designer for chiplet-based AI and High-Performance Compute silicon development. What You’ll Do Define on-chip fabric topologies connecting the multiple subsystems Specify the data-path fabric for the high-bandwidth routes: bandwidth provisioning, pipeline depth, buffering strategy, and back-pressure propagation between major subsystems. Architect the register-access fabric with address decoding and access-protection logic. Define the arbitration and QoS policy for shared fabric resources: priority assignment per traffic class, bandwidth reservation, and starvation-prevention mechanisms. Own the fabric error-handling architecture: how illegal accesses, timeouts, and protocol violations are detected, logged, and reported to the management subsystem. Own the CDC strategy for every clock-domain boundary on the die — and documenting the timing constraints for each. Own or closely review all fabric RTL: bus bridges, async FIFOs, arbiters, address decoders, and pipeline registers that form the on-chip interconnect. Drive integration assembly: own the top-level connectivity netlist that instantiates all major blocks and wires them through the fabric, serving as the integration point of truth. Coordinate with subsystem leads align on interface protocols, handshake semantics, and reset sequencing at each fabric boundary. Define and own the fabric performance model: estimate bandwidth utilization per path under representative traffic mixes for each operating mode and identify bottlenecks. Establish fabric-level bring-up tests: register accessibility checks, path connectivity tests, and loopback sequences that confirm the interconnect is healthy before full subsystem integration testing begins. Coordinate with the physical design team on fabric floorplan implications: block placement driven by dominant data flow, clock-region boundaries, and wire-length budgets for timing closure. What We’re Looking For BS/MS in Electrical Engineering, Computer Engineering, or equivalent with 8+ years of digital IC design, with at least 4 years owning on-chip interconnect, bus fabric, or NoC architecture at block-lead or integration-lead level. Deep expertise in one or more on-chip interconnect protocols: AXI4 / AXI4-Lite / AXI-Stream; CHI or equivalent; able to write and review bus bridge RTL and understand ordering rules, response channels, and error signaling. Experience with Network-on-Chip (NoC) design or integration of commercial NoC IP (in a complex SoC). Familiarity with AMBA CHI or ACE coherency extensions and their impact on fabric design. Solid understanding of CDC design: async FIFO design, gray-code counters, synchronizer topologies, and CDC verification methodology. Experience owning the top-level integration netlist or chip-level assembly RTL on a multi-block design. Strong SystemVerilog skills: arbiters, FIFOs, pipelines, address decoders, and parameterized bus infrastructure. Experience with static timing constraints for multi-clock designs Good To Have Background with high-speed chiplet or SoC integration at advanced nodes (7 nm or below), including floorplan-driven bus topology decisions. Experience building or maintaining an automated register-map generation flow (SystemRDL, IP-XACT, or similar). Prior role as chip-level integration lead responsible for assembling subsystem IPs into a complete design. Familiarity with hardware security primitives: access control, firewall IP, or trusted execution region isolation in the fabric. Experience with formal property verification of bus protocols or CDC crossings. Location Hybrid/On-site - San Jose, CA / Remote -USA