Director, RFS

Ref. ID: CTO/CT/RFS/2320 Location: Hong Kong Applied Science and Technology Research Institute (ASTRI) is founded in 2000 by the Government of the Hong Kong Special Administrative Region. As Hong Kong’s largest government-funded research and development centre, ASTRI is a key force and super‑connector driving innovation and technology advancement in Hong Kong, the Greater Bay Area, and the global innovation ecosystem. This role is strengthened through its merger with Nano and Advanced Materials Institute (NAMI). Committed to bringing high‑impact research from lab to market, ASTRI advances interdisciplinary, market‑driven R&D that delivers practical innovations for industry and meaningful benefits for society. Its technological strengths and capabilities enable AI‑powered, cross‑disciplinary ICT and advanced materials solutions across Smart City, Financial Technologies, Digital Health and Life Sciences, New Industrialisation and Intelligent Manufacturing, Application-Specific Integrated Circuits (ASIC) and Advanced Electronics, New Energy and Energy Storage, and Green and ESG Technologies. Over the years, ASTRI has cultivated a strong pool of I&T talent and earned numerous international awards for its pioneering innovations and contributions to industry and the community. Following the merger with NAMI, ASTRI’s cumulative global patent portfolio has grown to over 1,500, with more than 2,200 technologies successfully transferred to industry. With enhanced scale and capabilities, ASTRI is uniquely positioned to elevate Hong Kong’s innovation capacity, accelerate technology commercialisation, and drive societal and economic progress through world‑class applied research. To support our constant endeavour to position Hong Kong as a world-class smart city and an international hub of innovation and technology, we are seeking qualified professionals to fill the following position(s): Job Responsibilities: Serves as the leader of Core Competency Group to lead and drive the architecture, design, and delivery of next-generation mmWave RFICs. This role combines deep technical leadership, hands-on design capability, and end-to-end ownership from concept to silicon. Lead & mentor RFIC engineers and technical leads. Define system and RFIC architecture for mmWave transceivers (24-60 GHz) and other RF projects. Lead advanced RFIC development, including direct conversion (zero-IF) architecture design: (IQ design and optimization, LO distribution and phase noise management, DC offset, LO leakage, flicker noise mitigation, IQ mismatch calibration strategies, Drive architecture trade-offs vs low-IF / superheterodyne designs. Design RF/ mmWave Circuits in RFIC: oversee and contribute to design of: LNAs, PAs, mixers, VCOs, PLLs, frequency synthesizers, phase shifters, beamforming front-ends. Optimize designs for: NF, gain, linearity, Power efficiency and thermal performance, transceivers, phased-array systems. Drive RFIC design flows using industry tools: (Cadence Virtuoso – schematic design & layout, SpectreRF for RF simulation, ADE Explorer/Assembler – design verification and corner analysis, Virtuoso Layout Suite – physical implementation), RF system simulation & Tools (SystemVue / MATLAB). Experience with EM simulation tools (packaging, interconnect, antennas). Validate parasitics, coupling, and mmWave layout effects, mmWave integration & packaging (antenna-in-package/ antenna-on-chip, beamforming arrays, RF-package co-design, interconnect modeling and loss optimization, thermal and reliability considerations. Perform verification & signoff (DRC/LVS tools, EM-aware design signoff for mmWave circuits, statistical analysis and Monte Carlo simulations Own silicon development & validation (full lifecycle: specification, architecture, design, tape-out & validation. Lead silicon bring-up and debug: mmWave measurement setups. Implement calibration strategies (DC offset correction, IQ imbalance calibration, LO leakage suppression). Drive yield improvement across Process, Voltage Temperature and process corners. Define best practices in: mmWave layout and routing, Substrate noise isolation, Modeling and verification. Interface with: System architects, DSP team, Packaging and antenna team, Foundries and external partners Secure R&D fundings. Develop and contribute to innovation & technical strategy in patents and publications, technology roadmap in RFICs. Job Requirements: PhD in Electrical/Electronics Engineering / RF / Microwave. More than 10 years RFIC design experience with proven record of multiple silicon tape-outs (RF/mmWave). Drive architectural thinking and system-level insight in RFIC. Proven ability to lead, mentor and scale engineering teams. Ability to drive first-time-right silicon, first-pass silicon success rate is desirable, with hands-on experience in CMOS technologies. Possess strong knowledge and expertise in mmWave RF designs with considerations of Direct conversion impairments: (LO leakage, Flicker noise (1/f), DC offsets, IQ imbalance) Advanced knowledge and skills of RF simulation (PSS, PNoise, Harmonics) and Layout parasitics and EM effects. Proficiency in Cadence (Virtuoso platform (schematic + layout), SpectreRF simulation (PSS/PNoise), EM tools (Cadence), DRC/LVS flows (Calibre) Proven ability to secure R&D fundings Industry and commercialisation experience in RFICs is desirable. Professional language skill in English & Putonghua is required. Cantonese speaking skill is desirable. Good leadership and communication skills. Overseas candidates are welcomed to apply, with sponsorship of employment visa for the right candidate. Live ASTRI values. The appointment will be on renewable contract terms with a competitive salary and performance-linked gratuity. Fringe benefits include paid leave, medical, insurance coverage and contribution to MPF. The incumbent will normally work a five-day week. For interested parties, please submit your application with detailed CV within two weeks of the post date. Applicants are encouraged to submit their applications as soon as possible. The review of applications will continue until the post is filled. The resume should not include any sensitive personal information such as ID card no. or travel document number, etc. Position offer is subject to the applicant’s experience and academic qualification. Only short-listed candidates will be notified. ASTRI reserves the right not to fill the position. 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