Location: Dallas (one year contract)
Role: VLSI RTL Design Engineer in USA
Number of requirements: 01
Duration : 10-12 Months
Experience Required:
- Minimum of 10 years of experience
- Experience in end to end IP design life cycle that includes spec finalization, Architecture, RTL Design, Synthesis, Lint
- Excellent understanding of IP integration into the SoC and supporting SoC teams with any issues related to IP integration
- Experience of design qualification standards like ISO 26262 is added advantage
- Experience working on many of the of the following IP s: PCIe, UCIe, DDR, MIPI
Responsibilities:
- Work with Marketing team during MRD finalization
- Develop detailed functional specification
- Develop synthesizable RTL in Verilog
- Ensure Lint clean RTL
- Develop unit level test benches and run unit tests
- Develop synthesis scripts and provide timing constraints to the SoC team
- Provide help to SoC integration team to integrate RTL into SoC
- Support SoC level RTL debugging for IP test cases
- Participate in functional safety review for relevant IP with the end customer
Location:
Dallas, Texas, USA (For exceptional candidate we can look at remote working and engineer visiting the customer once in a month for reviews)
Visa/ Work Authorization Requirements if any:
Valid USA H1B visa with at least 1 year validity or USA Green Card Holder or USA citizen
Skills;
PCIe
UCIe
DDR
MIPI
Contact
Uday
muday_bhaskar@yahoo.com
Mulya Technologies
"Mining the Knowledge Community"