Job Description

Define or contribute to DFT design specifications and DFT strategy to meet test coverage, test time, and test cost targets; provide technical solutions for project requirements and issues.
Perform and review DFT implementation and verification activities.
Define and review DFT timing constraint (SDC) strategy, including test clocks and scan shift/capture requirements where applicable.
Generate, validate, and debug test patterns for simulation and tester/ATE use.
Mentor junior engineers; for Leader-level candidates, provide technical guidance and coordinate team activities.
Collaborate with FE/BE and related teams to complete chip design and test activities within the project schedule.

Requirements

Bachelor's or Master's degree in Electrical Engineering or Electronic Engineering.
5+ years of relevant experience in DFT, digital IC design, or a related area, including solid hands-on DFT experience.
Strong hands-on experience in core DFT activities, including scan insertion/compression, ATPG, and pattern verification/debugging. For Leader-level candidates, hands-on experience across the full core DFT flow is required, including scan insertion/compression, ATPG, MBIST, boundary scan/JTAG, pattern verification/debugging, and DFT timing.
Experience with one or more EDA tools from Synopsys, Cadence, Siemens EDA, or equivalent is preferred.
Experience in related digital design activities such as RTL design, synthesis, STA, clock/reset design, or logic verification is a plus.
Ability to communicate clearly and effectively within engineering teams and with global customers.
For Leader-level candidates, experience in technical mentoring, task coordination, planning, or project ownership is preferred.

Benefit & Perks

Join a supportive and motivated team where your contributions truly matter. As part of our long-term assignment in Japan, you’ll enjoy a range of benefits designed to support both your professional and personal life:

Housing Allowance: Company sponsored accommodation options or a monthly rental allowance.
Transportation Allowance: Reimbursement for commuting expenses.
Performance Bonuses: Based on your contributions and company performance.
Comprehensive Insurance: Full social and medical coverage in accordance with Japanese labor laws.
Home Visit Allowance: Financial support for travel back home.
Family Allowance: Additional benefits for employees and dependents in Japan.

Contact point

If you are interested in this position, please send your resume and cover letter to email: huongvt23@fpt.com (Ms. Thu Huong – Mobile phone: 036.390.4039).