Senior Verification Engineer - MEMS / UVM / SystemVerilog

Senior Verification Engineer - MEMS / UVM / SystemVerilog

We are currently partnered with a global leader in advanced MEMS-based programmable semiconductor solutions transforming the timing industry. They are looking to expand their team with an experienced verification engineer to work on the development of MEMS timing ICs.

This is a permanent position based in Delft, The Netherlands. (Visa Sponsorship available)

Key Responsibilities:

• Develop SV-RNM models for analog and mixed-signal circuits
• Own verification plans based on chip/block specs
• Build and maintain UVM-based environments (scoreboards, sequencers, monitors)
• Drive digital-top verification and define SystemVerilog Assertions (SVA)
• Write functional coverage models and covergroups
• Execute simulations and debug testbench failures
• Collaborate cross-functionally with design, test, and other verification teams
• Review and validate verification results for tape-out sign-off

Key Requirements:

• 5+ years post Masters or 8+ years post Bachelors in semiconductor verification
• Proficiency in SystemVerilog and UVM methodology
• Experience with scripting languages (Python, Perl)
• Strong command of SystemVerilog Assertions (SVA)
• Familiarity with analog schematics and Cadence Virtuoso

Keywords: SystemVerilog / UVM / AMS Verification / SV Assertions / MEMS / Mixed-Signal / Digital Design / RNM / Python / Perl / Cadence Virtuoso / Semiconductor / FPV / Datapath Verification / C++ / ASIC / RTL

If you are interested in this Senior Verification Engineer position, please send a copy of your CV to [email protected]

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