Analog Engineer

Job Description

Analog Layout Engineer

Location: Remote | Hybrid | Bengaluru

Experience

5+ Years

Joining Timeline

Immediate to 60 Days

Role Summary

We are seeking a highly skilled Analog Layout Engineer with strong expertise in advanced CMOS technology nodes to join our VLSI design team. The candidate will be responsible for delivering robust, high‑performance analog, mixed-signal, and high-speed layouts while working closely with design, verification, and global engineering teams. This role demands deep technical expertise, strong ownership, and the ability to execute complex layouts independently.

Key Responsibilities

• Develop high-quality analog, mixed-signal, and high-speed layouts for advanced CMOS technologies.
• Perform complete layout activities including floorplanning, placement, routing, matching, shielding, and optimization.
• Execute and debug DRC, LVS, ERC, and resolve complex physical verification issues.
• Implement advanced layout techniques to meet performance, power, area (PPA), reliability, and manufacturability requirements.
• Address FinFET-specific challenges, including restrictive DRC rules and advanced node limitations.
• Work closely with circuit designers to optimize layout for noise, matching, parasitics, and yield.
• Lead layout blocks or modules independently and drive them to tape‑out readiness.
• Collaborate effectively with global cross‑functional teams across geographies.
• Contribute to continuous improvement of layout methodologies and best practices.
• Hands-on experience or strong familiarity with GlobalFoundries (GF) process nodes, including FinFET technologies and lower geometry nodes, covering analog/mixed-signal design challenges, device characterization, and performance optimization.

Technology & Domain Expertise

• Hands-on experience in Analog / Mixed-Signal / High-Speed layout design.
• Strong exposure to advanced technology nodes, including:
• TSMC 2nm, 3nm, 5nm, 7nm, 14nm
• Solid understanding of physical and electrical effects, parasitics, EM/IR, and reliability considerations.
• Sound knowledge and hands-on experience in FinFET technology, layout design challenges, and DRC constraints.
• Experience working on lower technology nodes with complex layout rules.

Tools & Technical Skills

• Proficient in:
• Cadence Virtuoso Layout XL / GXL / EXL
• Cadence IC 12.1
• Calibre Physical Verification Flow
• Minimum 3+ years of experience using layout design and verification tools such as Cadence, LVS, RMAP, or equivalent.
• Strong debugging and problem‑resolution skills in physical verification.
• Scripting knowledge in SKILL, Perl, and Shell is an added advantage.

Education & Experience Requirements

Candidates should meet one of the following criteria: Associate’s Degree in Computer Science, Mathematics, Electrical Engineering, or related field + 5+ years of experience designing custom layouts in analog, mixed-signal, RF, or digital domains

Preferred Qualification:

• Bachelor’s degree in Electrical or Electronics Engineering (or equivalent)
• 5 to 8 years of experience in High-Speed / Analog / Mixed-Signal layout design in advanced or lower technology nodes.

Soft Skills & Competencies

• Strong communication and collaboration skills
• Proven ability to work effectively with global engineering teams
• Excellent analytical and problem-solving abilities
• Ability to lead projects independently and coordinate with team members
• Self-motivated, detail-oriented, and quality focused

Why Join Us

• Opportunity to work on cutting-edge semiconductor technologies
• Exposure to industry-leading advanced nodes
• Collaborative and engineering-driven work culture
• Clear ownership, technical growth, and leadership opportunity.

Interested Please Dm or share your resume at bsn.bhargava@sasken.com