Application Specific Integrated Circuit Design Engineer

Job Title: ASIC Physical Design

Job Location: Cork, IRL

Job Type: Full-time contract, Until 08/31/2027

Work Model: Remote

Summary:

• Extensive work experience in timing related activities and responsibilities such as library, LVF, AOCV/POCV/SOCV …etc.

• Experience in CAD tools including correlation between different timing sign-off tools vs. Spice simulation across different metrics such as timing, noise, monte-carlo, etc.

• Deep understanding of library characterisation process and flow with hands on experience on standard cell library characterisation.

• Strong ability in automating and developing new flows to improve overall productivity of the team using Python, Perl, TCL, Bash … etc.

• Working knowledge of Spice extraction, modelling and aging reliability model for latest technology nodes.

• Proven knowledge of latest technologies nodes and practices in physical design including Place and Routs (P&R) and Static timing analysis (STA) sign-of.

• Be willing to learn and involve in developing and validating new methodologies.

Required:

• 1-3 years of experience in Characterization, timing, power and pin-cap lib modeling for Analog and GPIOs. Functional understanding of GPIO / analog IPs as above for Characterization. • Preferable Experience with characterization tool and simulators like Silicon Smart, Hspice, Primesim, AFS, Spectre and Liberty format description. Self-motivation, teamwork, and strong communication skills. Scripting skill set will have added value

1) Python based programming

2) ASIC Physical Design

3) DesignCompiler, IC Compiler II (ICC2), FusionCompiler, PrimeTime, StarRC, Innovus, Synthesis, Floorplanning, Power Planning, Placement, CTS, Routing, STA