CPU DFT Engineer
- Salary
- $140K–$250KUSD per year
- Hiring from
- United States
- Work type
- Hybrid
- Posted
- Oct 2, 2026
Full-time · Multiple Levels · Austin and Santa Clara
THE ROLE
As a CPU DFT Engineer, you will participate in the following areas:
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Defining and implementing area and power efficient DFT architecture while collaborating with design, STA and PD
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Develop scan and BIST insertion flows, implement DFT registers in design blocks
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Completing DFT architecture specifications
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Review and integrate third party IPs into DFT architecture
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Define verification plans for DFT features
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Review DFT coverage for scan and MBIST
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Verification of DFT features in RTL and gates, and power aware simulations
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Generate test content for silicon bringup, and support silicon bringup activities including yield analysis
REQUIREMENTS — MUST TO HAVE
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BS or MS with 7+ years experience in DFT or DFT verification
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Scan or MBIST with industry standard EDA tools, or experience with DFT verification flows
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For scan role, able to define scan insertion, scan compression, and clocking requirements, and define intest and extest modes
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For MBIST role, be very familiar with memory repair, and repair interaction with functional operation
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Strong understanding of JTAG, IEEE 1500 and IEEE 1687
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Experience with Verilog RTL and gate level netlists, including running and debugging simulations
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Strong communication skills and ability to work with cross functional teams
REQUIREMENTS — NICE TO HAVE
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Using DFT features to support system debug
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Leveraging AI tools to accelerate DFT work flows
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Porting test content and supporting silicon bringup on ATE platforms
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Experience in Perl, Python, or TCL