CPU RTL Microarchitecture/Design Engineer - Full Time

What you'll do

• Design and implement CPU functional blocks based on microarchitecture specifications
• Develop, debug, and optimize RTL using SystemVerilog/Verilog
• Analyze performance, timing, area, and power tradeoffs and propose improvements
• Work with verification engineers to develop test plans and achieve functional coverage
• Partner with physical design engineers on area, timing, and power goals
• Participate in microarchitecture and RTL design reviews and write technical documentation

What we're looking for

• Bachelor's or Master's degree (or near-term graduation) in one of:
  • Electrical Engineering
  • Computer Engineering
  • Computer Science
  • A related field
• Strong foundation in computer architecture and digital design, with solid understanding of at least two of the following:
  • Out-of-order execution
  • CPU front-end / control logic
  • Load/store and memory systems
  • Cache hierarchy and coherency
  • Virtual memory
  • Floating-point / computer arithmetic
  • SIMD / vector processing
• Working knowledge of a modern ISA
• Hands-on Verilog/SystemVerilog experience, including:
  • RTL simulation
  • Testbench-based debugging
• Familiarity with the ASIC design flow:
  • RTL design
  • Verification
  • Synthesis
  • Timing analysis
• Scripting experience for automation, test generation, or data analysis, such as: Python, Perl, Tcl or C/C++