DFX Lead Engineeer

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About this opportunity

Senior DFX Lead
Ericsson Silicon | ASIC Development

Location: Austin, Texas Hybrid, On-Site work schedule

Ericsson's Radio and Baseband products run on ASICs we design ourselves, at the most advanced process nodes, and every silicon must be testable, debuggable, and observable throughout its life in the field. The Austin DFX & SLM team owns that capability for every ASIC across Ericsson's product line - DFX, Silicon Lifecycle Management (SLM) and Reliability, Availability and Serviceability (RAS) - from requirements and architecture through IP and SoC integration to silicon bring-up and in-field operation. The team holds tape-out gate authority for DFX and SLM scope on every program.
As Senior DFX Lead, you are the technical owner of DFX and RAS for one or more ASIC programs. You set the DFX architecture and test strategy, drive IP and SoC-level integration with design and physical-design teams, own pattern delivery to test engineering, lead the design side of silicon bring-up and yield learning, and carry the same hooks into in-field test, monitoring, and repair. Unlike a typical ASIC house where DFX ends at pattern hand-off, here you design for the whole lifecycle - manufacturing test, SLM and in-field RAS - from day one, and what you architect is reused across programs and product generations.
What you will do
• Own DFX and SLM architecture for one or more ASIC programs: the DFT plan, the test strategy, and the RAS requirements (fault detection, isolation and logging; in-field self-test; self-healing and repair; event routing from chip to board). Sign off DFX and SLM scope as a precondition for tape-out.
• Architect and drive the full DFX/SLM stack: scan and compression, ATPG, memory and logic BIST (with memory repair), JTAG/IJTAG and boundary scan (IEEE 1149.1, 1149.6, 1687), in-field test, and test access for custom, analog, and high-speed IP.
• Integrate DFX into RTL at IP and SoC level, own DFX timing constraints (SDC), and partner with physical design on implementation and timing sign-off.
• Own DFX/SLM verification: define and execute RTL and gate-level verification of the DFT, debug, and lifecycle-monitoring infrastructure across production-test and in-field use cases, including DFT rule checks and equivalence checking.
• Deliver test content to test engineering and silicon partners: pattern generation, fault simulation, coverage closure (structural, at-speed, functional) and test-time optimization; review test quality against DPPM targets with ASIC vendors.
• Define on-die debug and observability (scan/array dump, register-state snapshot on functional fail) and lead the design side of bring-up, yield learning and failure analysis, closing the loop into the next tape-out.
• Shape the SLM architecture with the SLM team and enable the runtime applications built on it (in-field monitoring, diagnostics, telemetry, adaptive power tuning) with systems, firmware and software teams - so lifecycle features are designed in at chip-spec time, not bolted on later.
• Advance the methodology: work with EDA vendors and CAD to define next-generation DFT flows and automate the DFX execution pipeline, so it scales across programs.
• Lead and grow the team: mentor DFX engineers, review their work, and represent DFX to architects, program management, and external partners across Austin, Sweden, and partner sites.

Join our Team

What you will bring
• 12+ years in SoC, IP, or ASIC design with an emphasis on DFX (DFT, DFD, DFM), including several years leading DFX on a complex SoC through tape-out on advanced process nodes.
• Minimum BSEE; MSEE preferred.
• Expert, hands-on command of the DFX stack - scan and compression, ATPG, JTAG/IJTAG, boundary scan, memory and logic BIST - and the trade-offs between test quality, test time and area, and their impact on implementation.
• Hands-on experience with a production DFT flow.
• Proven ownership of SoC-level DFT planning, architecture and execution, and of DFX verification (memory BIST, JTAG, boundary scan, in-field tests, custom IP test interfaces).
• Post-silicon experience: bring-up, yield learning, test-time reduction, and pattern delivery, working closely with test and product engineering.
• Working knowledge of RTL (Verilog/SystemVerilog), synthesis, STA and clock/reset design, and of physical-design and timing-closure flows so DFT integrates cleanly.
• Ability to lead through influence: set direction, review others’ work, and be the DFX voice to architects, program management, and external partners, with clear written and spoken communication across sites and time zones.
Nice to have
• RAS and SLM depth: on-die sensors and monitors, fault logging, telemetry, in-field diagnostics, and the firmware/SDK that reads them.
• DFT for chiplet, 2.5D or 3D designs (e.g., IEEE 1838).
• System-level test (SLT) methodology and functional ATE pattern enablement.
• Functional-safety or RAS experience on high-reliability products.
• Experience partnering with external ASIC vendors on DFT, test content and test quality.
• Background in wireless infrastructure, networking or compute ASICs.
Why join Ericsson
Your work ends up in networks that connect billions of people - and you see your designs through from requirements to working silicon in the lab, in production test, and in the field for years afterward. You will own DFX, RAS, and SLM architecture that is reused across every ASIC in the product line, working beside engineers who built this capability from the ground up, in a global team with a speak-up culture and a real commitment to work-life balance.
What happens once you apply
We encourage you to apply even if you don't meet every criterion. We value transferable skills and support continued development. Diversity and inclusion are core to our values, and collaboration across different experiences drives the innovation essential to our growth. Ericsson is proud to be an Equal Opportunity Employer. To prepare for the next steps, please explore the Ericsson hiring process.