Microelectronics Chief Engineer

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MITRE’s Electronic Systems Development department seeks a Microelectronics Chief Engineer to provide technical leadership for the microelectronics capability within the Signals & Electronics Division. The department develops and demonstrates microelectronic systems for sensing, communications, navigation, and other national security missions. Working with the Microelectronics Capability Steward and Division Chief Engineer, you will connect sponsor needs with technical strategy, rigorous engineering, research, laboratories, and reusable assets.

Roles & Responsibilities:

As Microelectronics Chief Engineer, you will guide the technical quality, mission relevance, and evolution of the microelectronics capability, aligned with division technical strategy and approved capability priorities. You will remain directly engaged in consequential sponsor work and provide independent technical judgment across projects and organizational boundaries. This Senior Principal role has no direct reports; formal delivery, staffing, and investment decisions remain with the accountable leaders.

• Develop and maintain the microelectronics technical roadmap with the Capability Steward, aligning it with division strategy, sponsor demand, technology trends, and lessons from direct work. Recommend research, workforce, laboratory, tool, and reusable-asset investments to the Division Chief Engineer and accountable leaders.
• Guide technical approaches and quality for microelectronics work, including requirements, architectures, design and verification methods, prototype evaluation, and readiness criteria. Convene technical reviews, engage relevant experts, assess evidence and risks, and recommend corrective action; ensure material concerns are addressed, documented, or escalated through established governance before delivery.
• Shape and contribute directly to sponsor work, translating mission needs into credible microelectronics approaches and prototypes. Integrate ASIC, FPGA, embedded systems, fabrication, test, and security expertise as needed; resolve technical interfaces and escalate consequential risks or conflicts beyond the capability’s scope to the Division Chief Engineer.
• Assess capability health using evidence of technical maturity, mission application, workforce depth, laboratory and tool readiness, utilization, and dependencies. Guide validation, modernization, adoption, and reuse of design methods, intellectual property, reference designs, test infrastructure, and other capability assets; recommend consolidation or retirement where warranted.
• Mentor engineers and emerging technical leaders through design reviews, actionable feedback, technical communities, and hands-on work. Promote interdisciplinary teaming, knowledge sharing, and engineering practice; advise department and division leaders on emerging skill needs and technical development opportunities.
• Communicate independent, evidence-based assessments of microelectronics technical health, mission impact, risks, and investment needs to the Capability Steward, Division Chief Engineer, and relevant project and sponsor leaders. Support capability governance while preserving the independence, objectivity, and technical credibility appropriate to MITRE’s FFRDC role.
• Identify research challenges arising from current and future sponsor needs. Shape experiments and research with MITRE teams and external partners, assess emerging semiconductor technologies and methods, and help transition promising results into sponsor work and reusable microelectronics capabilities.

Basic Qualifications:

• Typically requires a minimum of 12 years of related experience with a Bachelor’s degree; or 10 years and a Master’s degree; or a PhD with 7 years’ experience; or equivalent combination of related education and work experience.
• Demonstrated deep expertise in microelectronics, with substantive technical contributions in ASIC or FPGA design and development, and sufficient breadth to evaluate system architecture, implementation, verification, and hardware integration tradeoffs.
• Experience guiding microelectronic systems through requirements, design, verification, and hardware evaluation, with the ability to identify technical risks and assess design evidence and readiness.
• Working knowledge of processor and programmable logic architectures, digital hardware interfaces, and hardware integration sufficient to guide multidisciplinary microelectronics engineering and assess system tradeoffs.
• Demonstrated technical leadership of multidisciplinary teams, including setting technical direction, evaluating architectures, conducting technical reviews, and resolving complex engineering issues across project or organizational boundaries.
• Experience assessing technical capabilities, identifying gaps, and developing roadmaps or investment recommendations tied to mission or customer needs.
• Experience drafting research proposals and seeking funds to develop a proof of concept to demonstrate the idea.
• Demonstrated ability to explain complex technical issues and tradeoffs, communicate independent technical judgment, and build productive relationships with technical teams, sponsors, and leaders.
• Experience mentoring engineers and strengthening technical practice through actionable feedback and knowledge sharing.
• Must have an active Top Secret/SCI U.S Government issued Security Clearance. Per the U.S. Government’s eligibility requirements, you must be a U.S Citizen to be considered for a security clearance.
• This position requires a minimum of 4 days a week on-site

Preferred Qualifications:

• Experience applying microelectronics to positioning, navigation, and timing (PNT), RF communications, radar, or sensor systems.
• Advanced degree in Electrical Engineering, Computer Engineering, or a closely related hardware engineering discipline.
• Experience with ASIC implementation and tapeout, semiconductor fabrication and foundry engagement, packaging, or silicon characterization; or expertise in microelectronics security, trust, and assurance.
• Experience developing reusable design IP, reference architectures, verification environments, or laboratory and electronic design automation (EDA) infrastructure used across multiple projects.
• A record of shaping sponsor work and research, building partnerships with government, industry, or academia, and transitioning prototypes or research results into mission use.

This requisition requires the candidate to have a minimum of the following clearance(s):

Top Secret/SCI

This requisition requires the hired candidate to have or obtain, within one year from the date of hire, the following clearance(s):

Top Secret/SCI

Salary compensation range and midpoint:

$202,000 - $252,500 - $303,000 Annual

Work Location Type:

Onsite

It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.

Commitment to Non-Discrimination

All qualified applicants will receive consideration for employment without regard to disability, status as a protected veteran or any other status protected by applicable federal, state, local or international law.

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