nist prep graduate student in security evaluation and mitigation of cross chiplet vulnerabilities in heterogeneous integration

This position is part of the National Institute of Standards (NIST) Professional Research Experience (PREP) program. NIST recognizes that its research staff may wish to collaborate with researchers at academic institutions on specific projects of mutual interest, thus requires that such institutions must be the recipient of a PREP award. The PREP program requires staff from a wide range of backgrounds to work on scientific research in many areas. Employees in this position will perform technical work that underpins the scientific research of the collaboration. Research Title: Security Evaluation and Mitigation of Cross-Chiplet Vulnerabilities in Heterogeneous Integration. The work will entail: This project directly addresses the semiconductor industry’s need for secure and trustworthy heterogeneous integration, aligning with national security priorities and trusted microelectronics goals. The work will entail:

• Research on threats to security of heterogeneous integration, including formal threat modeling, metrics for evaluating security leakage and mitigation effectiveness, and attack simulations.
• Research and develop a security evaluation framework for identifying and characterizing vulnerabilities across chiplets, inter-chiplet interfaces, shared interconnects, memory controllers, and other system-level resources.
• Engage stakeholders across industry, academia, and government to align security requirements, research priorities, evaluation methods, and adoption pathways, incorporating insights from workshops and ongoing collaborations.
• Focus on emerging areas such as advanced packaging and chiplet-based systems, developing actionable countermeasures and publishing findings for industry use.
• Identify, research, and document methods to support secure and interoperable security assessment across heterogeneous integrated systems, including benchmarks, test methodologies, metrics, and machine-readable reporting formats suitable for large-scale deployment.

Key responsibilities will include but are not limited to:

• Developing a security evaluation and mitigation framework for heterogeneous integration, with an initial focus on multi-tenant computing platforms.
• Addressing emerging vulnerabilities across chiplets, interposers, interfaces, and integrated components, while enabling trusted, scalable, and privacy-preserving communication within heterogeneous systems.
• Developing and evaluating practical mitigation techniques that reduce security leakage while preserving system performance, scalability, and design flexibility across different chiplet architectures, interconnect topologies, and integration configurations.
• Documenting results and developing publishable material for consumption by semiconductor engineers.

• Presenting results at internal meetings, and occasional meetings with external stakeholders.

Qualifications

• Enrolled in a PhD program in Computer Engineering, Computer Science, Electrical Engineering, or a related field.
• Familiarity with integrated circuit design and threat analysis methodologies.
• Strong technical expertise in general-purpose programming languages, including C/C++, Python, and MATLAB, as well as hardware description languages widely used in the semiconductor industry, such as Verilog HDL.
• Expertise in open-source computer architecture and interconnect simulation tools, including gem5, Noxim, Sniper, and LegoSim, as well as leading commercial design and verification tools from Cadence and Synopsys, such as Cadence Innovus and Synopsys Design Compiler.
• Knowledgeable in Cybersecurity tenets.
• Ability to integrate information from diverse sources effectively and efficiently.

• Strong oral and written communication skills.
• US citizenship is preferred

Privacy Act Statement Authority: 15 U.S.C. § 278g-1(e)(1) and (e)(3) and 15 U.S.C. § 272(b) and (c) Purpose: The National Institute for Standards and Technology (NIST) hosts the Professional Research Experience Program (PREP) which is designed to provide valuable laboratory experience and financial assistance to undergraduates, post-bachelor’s degree holders, graduate students, master’s degree holders, postdocs, and faculty. PREP is a 5-year cooperative agreement between NIST laboratories and participating PREP Universities to establish a collaborative research relationship between NIST and U.S. institutions of higher education in the following disciplines including (but may not be limited to) biochemistry, biological sciences, chemistry, computer science, engineering, electronics, materials science, mathematics, nanoscale science, neutron science, physical science, physics, and statistics. This collection of information is needed to facilitate administrative functions of the PREP Program. Routine Uses: NIST will use the information collected to perform the requisite reviews of the applications to determine eligibility, and to meet programmatic requirements. Disclosure of this information is also subject to all the published routine uses as identified in the Privacy Act System of Records Notices: NIST-1: NIST Associates. Disclosure: Furnishing this information is voluntary. When you submit the form, you are indicating your voluntary consent for NIST to use of the information you submit for the purpose stated. SURA is an Equal Opportunity Employer. We believe that no one should be discriminated against because of their differences, such as age, disability, ethnicity, gender, gender identity and expression, religion, or sexual orientation. All employment decisions shall be made without regard to age, race, creed, color, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status, or any other basis as protected by federal, state, or local law. PREP0005231

Work Type: Remote