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Packaging SI/PI Engineer (Senior/Staff/Senior Staff/Principal)

Analogue InsightEngineering & Development
Hiring from
United Kingdom
Work type
Remote
Posted
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THE COMPANY
Established in early 2024, at Analogue Insight we are bridging the Analogue and Digital Worlds for Tomorrow through our Chiplet Solutions. Our core expertise lies in developing cutting-edge Chiplet technology that serves as the building block for advanced communication systems. Our Chiplets are designed to offer high performance, scalability, and integration flexibility, enabling our clients to achieve breakthroughs in computation speed, data processing, and connectivity. For more information about us, check out our website (Analogue Insight) and LinkedIn Page (Analogue Insight™: Overview | LinkedIn).

THE ROLE
We are seeking a highly skilled and experienced Analog Design Engineer to play a key role in architecting and delivering high-performance serial links for our state-of-the-art solution. You will directly shape the analog architecture of customer-facing chiplet IP, influencing performance, scalability, and roadmap decisions. This role is well suited to engineers with a strong level of technical ownership who enjoy deep, hands-on work in a small, high-impact team.
Hiring Manager: Christian Borelli, Founder and CSO.

KEY RESPONSIBILITIES

  • SI/PI & Package Co-Design for Advanced Systems:
    Lead signal and power integrity analysis and package co-design for advanced chiplet-based systems, including HBM, UCIe die-to-die links, high-speed SerDes, and Co-Packaged Optics (CPO). Drive design decisions across 2D, 2.5D, and 3D integration technologies.

  • System & Package Architecture Definition:
    Collaborate with silicon, system, and product teams to define package and interconnect architectures, contributing to early-stage floor-planning, bump maps, routing strategies, and PDN topologies, balancing performance, power, area, thermals, and manufacturability.

  • High-Speed Interconnect & Wiring Studies:
    Perform detailed wiring, interposer, and substrate studies to determine optimal routing, reference structures, power distribution, and package sizing for multi-die systems, supporting UCIe, HBM, and high-bandwidth SerDes interfaces.

  • SI/PI Simulation & Modelling:
    Conduct extensive electromagnetic, circuit-level, and system-level simulations to validate signal integrity, power integrity, and noise performance, including:

    • PDN impedance, IR drop, and simultaneous switching noise for HBM and logic dies

    • Package-to-die interactions in CPO and optical-electrical interfaces

  • Design Optimisation & Verification:
    Identify and implement optimisation strategies to improve eye margin, jitter, BER, power delivery stability, and EMI, ensuring designs meet aggressive performance targets across process, voltage, and temperature corners.

  • Cross-Functional Technical Leadership:
    Act as a key technical interface between package design, silicon design, SI/PI, optics, and system teams, providing analysis-driven recommendations and guiding design iterations from concept through sign-off.

  • Design Guidelines & Documentation:
    Develop and maintain package co-design guidelines, SI/PI methodologies, and best-practice documentation, supporting scalable reuse across platforms and future programs.

  • Technology & Industry Awareness:
    Stay current with emerging trends in advanced packaging, chiplet standards, UCIe evolution, HBM roadmaps, and CPO architectures, maintaining awareness of competitive solutions and KPIs.


WHAT WE’RE LOOKING FOR

  • Master’s, or Ph.D. in Electrical Engineering or a related field, with a focus on signal integrity, power delivery, or high-speed hardware design.

  • Strong expertise in SI/PI fundamentals, including transmission lines, impedance control, crosstalk, jitter, PDN design, and noise coupling.

  • Hands-on experience with advanced packaging technologies (2D, 2.5D interposer, 3D stacking) and chiplet-based architectures.

  • Experience analysing and optimising HBM interfaces, UCIe die-to-die links, and high-speed SerDes channels.

  • Familiarity with co-packaged optics (CPO) concepts and electrical-to-optical interface considerations.

  • Proficiency with SI/PI and EM simulation tools such as Ansys HFSS, HSPICE, Keysight ADS, and Cadence Sigrity.

  • Solid understanding of circuit extraction techniques and correlation between EM and circuit-level simulations.

  • Excellent analytical and problem-solving skills with strong attention to detail.


Soft & Professional Skills:
  • Clear, structured communication in professional English—able to explain complex results concisely
  • Collaborative and feedback-oriented mindset
  • Demonstrated ability to mentor and guide less experienced engineers
  • Strong ownership, reliability, and follow-through
  • Curious, self-motivated attitude, eager to learn and explore new tools or methods
  • High level of integrity and professionalism in representing the company and handling sensitive information.

OUR CULTURE
We’re a fully remote team of around 25 people distributed across the UK, Armenia, Italy, the US, Estonia, India, and beyond. We believe great talent is everywhere!
  • Our values are our north star: We Grow Together, We Win Together. Excellence Builds Relationships. Trust Is Our Currency. Results Matter, but People Create Them.
  • Connected, even remotely: We invest intentionally in staying connected through regular all-hands, 1:1s, technical reviews, and informal coffee chats, so collaboration feels natural and human despite the distance.
  • High ownership, real impact: Everyone contributes directly to customer-facing IP. Your work doesn’t disappear into layers of management – it ships.
  • How we work: We move fast but thoughtfully, communicate openly, and balance autonomy with support. Technical decisions are debated openly and grounded in data, trade-offs, and first-principles thinking.

WHY JOIN US
  • Remote-first flexibility – work from anywhere, with flexible hours
  • Equipment & setup – we’ll provide the tools you need to succeed
  • High-impact projects – design real analog IP used in customer silicon
  • Supportive team culture – a dedicated manager and a team of colleagues ready to help
  • Competitive, transparent compensation – adjusted for your location and engagement model
  • Learning & growth – AI–DLP sessions, technical deep dives, and peer-led knowledge sharing that build both technical depth and system-level perspective

RECRUITMENT PROCESS
  1. Founder Call (30 min) – mutual introduction and interest alignment
  2. Technical Interview (90 min) – fundamentals, reasoning, and problem-solving
  3. Optional: Second Technical Interview (60 min) – another deep-dive into specific topics, which might include a presentation that we'll let you know about in advance
  4. HR & Culture Call (45 min) – values, collaboration style, and ways of working
  5. Offer & Next Steps – we send the offer and kick off the onboarding process.

Disclaimer: This is our standard process for most roles. For more senior, specialized, or higher-authority positions, we reserve the right to amend or tailor these steps as we see fit.

If you don’t meet every requirement but feel excited about the role, apply anyway. We value curiosity, integrity, and potential as much as experience.

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