Power Management Architect

RosaicLabs is seeking a Power Management Architect to define power architecture across its multi-die computing systems. You will lead rail and voltage-domain planning, SoC and package power delivery, and the control flows that balance performance, efficiency, thermals, and reliability. The role spans architecture through implementation and validation, working closely with silicon, package, platform, firmware, and performance teams.

• Define the system power architecture and allocate power budgets across compute chiplets, I/O dies, memory interfaces, high-speed links, and the package.

• Own the rail plan and voltage domains. Specify current, transient, droop, sequencing, and monitoring requirements for each domain.

• Work with package and platform teams to evaluate board-level and in-package voltage regulation, including regulator placement and control, rail entry, power distribution, and thermal constraints.

• Specify power-on, ramp, boot, reset, shutdown, idle-entry, and fault-recovery flows, including dependencies among regulators, clocks, sensors, the central power controller, and distributed power agents.

• Architect power-management control and communication across dies, including controller and agent responsibilities, control paths, and failure handling.

• Define dynamic voltage and frequency scaling, clock and power gating, package idle states, and memory low-power transitions while accounting for wake latency and performance impact.

• Define package power-cap enforcement, thermal throttling, fast response to droop or overcurrent, and limits on rapid changes in current draw.

• Specify host, BMC, operating-system, and firmware interfaces for power caps, performance controls, telemetry, and emergency responses.

• Develop activity-based power models and energy estimates to guide architectural tradeoffs and verify power budgets.

• Establish verification and validation requirements for power states, transitions, faults, and recovery, including power-aware simulation and UPF-based checks.

• Bachelor’s degree in electrical engineering, computer engineering, power electronics, or a related field, or equivalent practical experience.

• At least 12 years of relevant experience in SoC power architecture, power delivery, or complex multi-domain power-management design.

• Direct experience defining rail plans, voltage domains, regulator requirements, and chip or package power budgets.

• Experience architecting power-state sequencing, DVFS, power caps, and thermal or electrical throttling.

• Experience carrying power-management requirements through implementation and verification in collaboration with silicon, package, platform, and firmware teams.

• Power architecture for multi-die packages, high-bandwidth memory or LPDDR interfaces, and high-speed I/O.

• Power-delivery analysis involving transient current, voltage droop, power integrity, and regulator tradeoffs.

• Microarchitecture of power controllers, distributed agents, sequencers, or telemetry logic.

• Activity-based power modeling, UPF, power-aware simulation, and silicon power validation.