Principal Engineer - Physical Implementation & Multi-Die Integration

At Euclyd, we build chips and systems that make advanced AI radically more energy-efficient and affordable. In September 2026, we closed a Series A of more than €200 million, co-led by Samsung, Somerset Capital Partners, the EQT-managed Scaleup Europe Fund and Innovation Industries. Now we’re growing fast across the full compute stack, from silicon to systems and software.

Our AI compute platforms are built on custom silicon, chiplets and advanced packaging. As Principal Engineer, Physical Implementation & Multi-Die Integration, you join our Silicon team and own the technical baseline for how our chips get from RTL to tape-out. You are Euclyd’s internal technical authority on physical implementation: you direct and critically review our external implementation partners, resolve the issues that cut across domains, and make sure every design is truly ready for sign-off and tape-out.

What you’ll do

• Own the implementation baseline: own physical implementation from RTL handoff through final sign-off and tape-out, and give clear recommendations on implementation readiness, technical risk and tape-out.
• Set the requirements: define and maintain the implementation requirements, including SDC timing constraints, clocking, resets, UPF power intent and physical design handoff criteria.
• Direct and challenge our partners: lead technical reviews with external implementation partners, question assumptions and results, spot risks early and drive them to resolution.
• Review the results that matter: assess implementation results across synthesis, floorplanning, timing closure, clocking, congestion, power integrity, physical verification and sign-off.
• Connect the domains: coordinate implementation-impacting decisions across architecture, RTL, verification, DFT, packaging, memory and IP integration.
• Be our technical counterpart: represent Euclyd in implementation-related discussions with EDA, IP, foundry, memory and other technology partners.
• Shape multi-die architectures: bring physical design expertise to our chiplet and multi-die architectures, including die partitioning, die-to-die interfaces, PHY integration and package-related constraints.
• Raise the bar: improve implementation methodologies, EDA flows and review practices, identify which capabilities we should build in-house, and mentor the engineers who will form our future Physical Implementation & Methodology team.

AI-native, for real

We build infrastructure for agentic AI, and we use AI the same way in how we build our own products. In physical implementation, that means much more than a chatbot next to your terminal. Think of AI agents that parse and compare timing reports across runs, flag regressions in congestion or IR drop overnight, cross-check partner deliverables against our handoff criteria, or draft constraint and flow scripts, so you can spend your time on the decisions that really matter.

At the same time, tape-out leaves no room for guesswork. You know when to trust a tool and when to dig into every path yourself, and you treat AI-assisted analysis with the same absolute care as your own. The goal: a small, highly leveraged team that keeps a firm technical grip on a large external implementation effort.

Good to know

This is first and foremost a hands-on Principal Engineer role with strong technical ownership. For now, much of the detailed implementation is done by external partners, and your job is to be the sharp, independent technical authority who steers and challenges them. As our internal silicon organisation grows, the role can grow with it: you may build and lead an internal Physical Implementation & Methodology team, adding people leadership to your technical leadership. The focus is on technical ownership and engineering leadership, not on overall program management, commercial supplier management or contract negotiations. If you come from a large corporate, expect fewer processes, much shorter lines to decisions and plenty of room to shape how we work.

What you bring

• Implementation track record: extensive ASIC physical design or implementation experience at Staff, Principal or Architect level, with multiple successful tape-outs to your name.
• Deep implementation knowledge: synthesis, floorplanning, static timing analysis, timing closure, clocking, power analysis and physical sign-off hold no secrets for you.
• SDC and STA expertise: a strong command of SDC and static timing analysis methodologies.
• Tool experience: hands-on experience with Synopsys and/or Cadence implementation and sign-off flows, such as Fusion Compiler, PrimeTime, Innovus and Tempus.
• Integration experience: integrating SRAM and memory macros, third-party IP, high-speed interfaces and PHYs, as well as UPF and low-power implementation.
• Technical leadership: the depth and confidence to technically direct and challenge external implementation partners, combined with strong hands-on debugging and problem-solving skills.
• AI-native mindset: you already use AI in your engineering work and you’re eager to see how far it can go, with a healthy dose of scepticism wherever sign-off is on the line.
• Languages: fluent English, spoken and written.
• Who you are: a first-principles thinker who operates independently in a fast-moving silicon development environment. You take ownership, believe in radical efficiency and treat every tape-out with absolute care.

Nice to have

• Chiplets and multi-die: experience with chiplet or multi-die architectures and die-to-die interfaces.
• Advanced packaging: experience with advanced packaging technologies and their impact on silicon implementation.
• Methodology: experience defining implementation methodologies and EDA flows.
• The semiconductor ecosystem: experience working directly with EDA vendors, foundries, IP providers, memory suppliers and other ecosystem partners.
• Growing people: experience mentoring engineers, developing technical capability or leading a small engineering team.

What we offer

The chance to help tackle the energy problem of AI, by building a disruptive AI compute platform from the logic gate up. You’ll be the technical authority on how our silicon is implemented, with real influence on architecture and methodology, in a small, agile and mission-driven team at the High Tech Campus Eindhoven, in the heart of Europe’s semiconductor ecosystem. We offer a competitive salary depending on your experience, plus holiday allowance, standard secondary benefits and the flexibility of hybrid working.

Interested?

Send a short introduction and your CV or LinkedIn profile to careers@euclyd.ai. Tell us why this role appeals to you, and about the toughest timing-closure or sign-off issue you ever resolved.