Principal Engineer – RV (EM/IR)

About TylSemi, Inc. The Opportunity The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package? That's what we solve. TylSemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale. This isn't a nice-to-have. It's the critical path. Why Now The Market Window The semiconductor industry is going through its biggest architectural shift in 40 years: • Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies. • Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually. • IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself. Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing. Culture & Team: How We Work No Politics, No Bureaucracy There are no layers, no approval chains, no corporate theater. • If you have an idea, we test it. If it works, we ship it. • No endless meetings, no PowerPoint presentations to convince middle management. Remote-Friendly, Global Team • US team: Bay Area preferred, but we hire the best people regardless of location • India team: Building a world-class design center in Bangalore Move Fast, Ship Real Products We're not a research project. We have paying customers, committed capital, and aggressive timelines. This is a company, not a lifestyle business. We're building to win. What We Value • Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it. • Bias for action. We move fast. Analysis paralysis doesn't fly here. • Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware. • Low ego, high standards. We don't care about titles or politics. We care about results. The Ask If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits. We're asking you to walk away from that and bet on us. Here's why you should: • The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building. • The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo. • The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue. • The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI. This is the bet. Join us and build something that matters. Or stay comfortable. No judgment. But if you're the kind of person who wants to take the shot, we'd love to talk. READY TO JOIN? Role Overview We are looking for an experienced Principal Engineer – RV (EM/IR) to lead power integrity and reliability signoff activities for advanced-node SoC designs. In this role, you will drive IR drop and electromigration (EM) analysis, define signoff methodologies, and collaborate with cross-functional teams to achieve robust and reliable silicon implementation. The ideal candidate should possess deep expertise in power integrity analysis, strong understanding of advanced-node challenges, and proven experience in leading signoff closure for complex chip designs. What You’ll Do Lead full-chip and block-level IR drop and electromigration (EM) analysis for advanced-node SoC designs Drive power integrity signoff closure by identifying, debugging, and resolving IR/EM violations Collaborate with Physical Design, Power, Package, and Foundry teams to optimize power delivery networks Define and improve EM/IR methodologies, automation flows, and signoff strategies Perform static and dynamic IR analysis across multiple operating conditions and scenarios Analyze power grid robustness, current density, and thermal impacts to ensure design reliability Support tapeout activities and ensure high-quality signoff delivery within project timelines What We’re Looking For Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or VLSI-related discipline 10+ years of experience in IR/EM analysis, power integrity, or Physical Design signoff Strong understanding of power integrity concepts including static/dynamic IR drop, EM analysis, and power grid optimization Hands-on experience with industry-standard tools such as Cadence Voltus, Ansys RedHawk, or equivalent Good understanding of Physical Design flow including floorplanning, placement, CTS, routing, and extraction Strong scripting skills in Tcl, Python, Perl, or Shell for automation and flow development Good to Have Experience with advanced technology nodes such as 7nm, 5nm, 3nm, or below Exposure to package-aware analysis, thermal analysis, and low-power methodologies Experience in leading signoff closure for large-scale SoC or high-performance compute designs Success in This Role Looks Like Achieving robust IR/EM signoff with minimal iterations and successful tapeout execution Early identification and resolution of power integrity risks impacting performance and reliability Improved signoff productivity through methodology enhancements and automation initiatives Strong technical leadership and collaboration across implementation and signoff teams Location Hybrid / On-site – Bengaluru