Senior ASIC / Custom Circuit Design Engineer Memory & Mixed-Signal

Senior ASIC / Custom Circuit Design Engineer Memory & Mixed-Signal 📍 Zurich | 🧠 Deep Tech | Advanced Nodes | 🏠 Hybrid We are partnering with an innovative Zürich-based tech company who are seeking a motivated Senior ASIC / Custom Circuit Design Engineer to design high-performance, low-power custom-digital and memory-centric circuits used at the heart of their compute architecture. This is a full-time permanently employed position. If you love circuit design, debugging silicon behaviour, and optimizing for power, speed, and stability this is for you. 👇 🚀 What you will be doing You will take designs from concept implementation characterization silicon bring-up. Key responsibilities include: 🧩 Designing custom circuits for SRAM, register files, datapaths & periphery 🧠 Architecting and implementing blocks on advanced nodes (FinFET, sub-10nm) 📏 Running corner, Monte-Carlo, variation, and stability simulations 🤝 Working closely with layout, digital, backend, DFT & verification teams 🚦 Reviewing extraction results, debugging EM/IR issues & proposing fixes 📐 Defining clean integration boundaries for digital-on-top environments 🧬 Supporting silicon correlation (bring-up, ATE analysis, errata handling) 🔧 Creating reusable design kits, models, testbenches & automation scripts 📝 Documenting methodologies and improving internal design flows 🌟 What you will bring (must-haves) The essentials for success in this role: 5+ years in custom digital, mixed-signal, or memory (SRAM) design Proven ownership of blocks through full design cycles Strong understanding of FinFET behaviour (variation, leakage, stability, periphery trade-offs) Hands-on experience designing memory sub-systems, datapaths, or register files Ability to analyze extraction/PEX results and work closely with layout Solid foundation in performance, power, and area (PPA) optimization Comfort with simulation flows, timing behaviour, parasitics, and correlation Good scripting knowledge (Python or Tcl) for automation Clear communication & strong documentation habits Nice to have (bonus skills) These are not required, but they will help you stand out: Experience with memory compilers or memory characterization flows DTCO/STCO exposure (device bitcell periphery understanding) Background in EM/IR analysis or reliability considerations Familiarity with custom-digital verification environments Knowledge of test structures, MBIST/scan concepts, or redundancy features A passion for hardware optimization and deep-dive debugging 🧩 Who this role suits Someone who: Loves hands-on transistor-level + custom-digital design Enjoys working on bleeding-edge nodes Wants visibility across architecture, circuit design, layout & silicon Appreciates a collaborative and high-impact hardware environment 🌍 Location & setup 📍 Zurich, Switzerland 🏠 Hybrid working model (onsite collaboration + home office flexibility)