Senior Design Engineer

Senior SoC FPGA Digital Design and Verification Engineer About Cohu Cohu is a global technology and market leader in semiconductor test and inspection metrology markets. Our advanced systems are critical to ensuring the quality and reliability of the next generation of electronics. This role is a key part of the team developing our state-of-the-art 26 GHz RF semiconductor tester platform , built around the cutting-edge Xilinx Versal Adaptive Compute Acceleration Platform (ACAP) . We need an expert to design and verify the high-performance digital logic that powers this platform. Learn more at cohu.com . The Role: High-Speed RTL and SoC Integration You will be responsible for RTL design , SoC integration , and high-speed timing closure of key digital blocks within the Xilinx Versal ACAP. This role sits at the intersection of hardware and software, requiring deep expertise in digital design best practices, advanced verification methodologies, and a functional understanding of Model-Based Design for DSP implementation. Key Responsibilities RTL Design and Implementation Develop and implement robust, high-performance RTL (Register Transfer Level) using Verilog or SystemVerilog for key functional blocks within the Versal ACAP. Focus on blocks related to high-speed data path, clocking, control, and interaction with the RF front-end. SoC Integration and Bus Interfacing Integrate complex IP blocks and custom logic within the SoC structure, managing data flow across the Versal’s Application Processor Fabric and Programmable Logic. Implement and configure AMBA AXI protocols (AXI4-Lite, AXI4-Stream, and AXI4-Full) for efficient system-level communication and data transfer. Verification and Testing Employ advanced verification techniques, including developing testbenches and components within the Universal Verification Methodology (UVM) framework. Define and implement verification flows that cover hardware/software co-verification, leveraging UVM-SW to test firmware access to custom hardware registers and logic. High-Speed Constraints and Timing Closure Define and achieve timing closure for high-frequency digital logic used within the 26 GHz RF system architecture. Analyze and resolve complex timing violations, managing clock domain crossings (CDC) and synchronous logic paths to meet stringent performance targets. Algorithm Implementation and Register Maps Implement DSP algorithms—often derived from MATLAB/Simulink models and auto-generated code—into optimized RTL structures. Design, document, and maintain Register Maps that serve as the interface between custom hardware and embedded firmware running on ARM processors within the Versal ACAP. Collaboration Work closely with Firmware Engineers, RF Engineers, and SoC Architects to ensure RTL, firmware, and analog interfaces align with system requirements. Required Skills and Experience RTL Development: Strong command of Verilog/SystemVerilog for high-speed, synchronous digital design. SoC Interconnects: Expert knowledge of the AMBA/AXI bus protocol and experience integrating IP cores into SoC architecture (preferably using Xilinx tools such as Vivado/Vitis). Verification: Experience with modern hardware verification methodologies, including UVM, constrained randomization, and coverage-driven verification. Experience with UVM-SW co-verification is highly desirable. Architecture Knowledge: Understanding of the underlying ARM architecture and its interaction with programmable logic fabric. High-Speed Design: Proven success in achieving timing closure in high-frequency designs; strong understanding of Static Timing Analysis (STA). Embedded Interfaces: Proficiency with standard serial interfaces such as I²C and SPI ; experience designing and managing detailed Register Maps . DSP Implementation: Knowledge of fundamental DSP concepts and experience translating high-level algorithms into efficient, fixed-point RTL. Model-Based Design: Experience using MATLAB/Simulink for modeling, simulation, and auto-code generation for hardware targets. Preferred Qualifications Experience with Xilinx Versal or Zynq UltraScale+ MPSoC devices. Experience with formal verification techniques. Exposure to high-speed protocols (e.g., JESD204, high-speed SerDes). Background in semiconductor test equipment or high-frequency instrumentation. RTL Design: Develop high-performance RTL using Verilog/SystemVerilog, focusing on key functional blocks and high-speed data path interaction. SoC Integration: Seamlessly integrate complex IP blocks and custom logic, managing data flow across the Versal's architecture. Bus Interfacing: Implement AMBA AXI protocols for efficient system communication, including AXI4 configurations. Verification: Employ UVM-based techniques, covering hardware/software co-verification, and define comprehensive verification flows. High-Speed Constraints: Achieve timing closure for the 26 GHz RF system, resolving timing violations and optimizing clock domains. Algorithm Implementation: Translate DSP algorithms from MATLAB/Simulink into optimized RTL structures, ensuring efficient performance. Register Maps: Design and maintain Register Maps for effective hardware-firmware communication and interface management. Collaboration: Work closely with Firmware, RF, and SoC teams to align RTL, firmware, and analog interfaces, ensuring system requirements are met. Documentation: Create detailed documentation for RTL design, verification processes, and project updates, ensuring knowledge transfer. RTL Development: Proficiency in Verilog/SystemVerilog for high-speed digital design is essential, with a strong command of RTL implementation. SoC Interconnects: Expertise in AMBA/AXI bus protocol and IP core integration, preferably with Xilinx tools like Vivado/Vitis. Verification: Extensive knowledge of UVM, constrained randomization, and coverage-driven verification, with UVM-SW co-verification skills. High-Speed Design: Proven ability to achieve timing closure in high-frequency designs, with a strong understanding of STA. Embedded Interfaces: Proficiency in I²C, SPI, and Register Map design, ensuring efficient embedded system communication. DSP Implementation: In-depth DSP knowledge and experience translating algorithms into efficient, fixed-point RTL. Model-Based Design: Proficiency in MATLAB/Simulink for modeling, simulation, and auto-code generation for hardware targets. Xilinx Experience: Prior work with Xilinx Versal or Zynq UltraScale+ is highly advantageous, providing a strong foundation. Formal Verification: Knowledge of formal verification techniques is a plus, enhancing the verification process. High-Speed Protocols: Exposure to JESD204 or high-speed SerDes is desirable, offering expertise in high-speed data transfer.