Senior Verification Engineer

Our RTL team delivers efficient ASIC and FPGA implementations of advanced communications algorithms, working across IP development, integration and verification. To support this work, we are looking for a Senior Verification Engineer to support the complete UVM verification of Accelercomm IP. Purpose Responsible for verification of RTL implementations for advanced wireless communications IP and modem subsystems, ensuring designs meet functional, performance and quality requirements prior to FPGA deployment and ASIC tape-out. Key Responsibilities Develop verification plans from design and architecture specifications. Create and maintain SystemVerilog/UVM verification environments. Develop testbenches, assertions, scoreboards and coverage models. Execute directed and constrained-random verification. Analyse coverage and debug RTL and verification issues. Support subsystem and system-level integration activities. Contribute to automation, regression and CI workflows. Participate in design reviews and verification sign-off. Mentor and support junior colleagues Skills, Knowledge & Expertise Required Degree in Electronic Engineering, Computer Engineering or a related discipline. At least 3 years experience verifying digital ASIC and/or FPGA designs. Strong SystemVerilog and UVM skills. Understanding of RTL design principles and hardware implementation. Experience with coverage-driven and assertion-based verification. Linux proficiency and scripting skills (Python, Tcl or Bash). Strong analytical, debugging and problem-solving skills. Experience using AI to accelerate verification without sacrificing quality Ability to work across multiple teams Desirable Experience in 4G/5G, NTN, satellite communications or DSP systems. Knowledge of modem architectures and Layer 1 processing. Experience with Formal Verification, FPGA prototyping and CI environments. Familiarity with MATLAB or equivalent modelling tools.