Silicon Power Engineer

RosaicLabs is seeking a Silicon Power Engineer to improve the power efficiency of its compute silicon. You will help define power-management features, build workloads that reveal how the design consumes power, and turn measurement and analysis into changes that improve performance per watt. This is a hands-on role working with architecture, verification, RTL, physical design, firmware, and silicon validation teams.

• Define and evaluate silicon power-management features, including clock gating, power gating, idle states, and dynamic voltage and frequency scaling. Specify expected power savings, performance impact, and conditions for entering and exiting each state.

• Develop representative, high-activity, and corner-case workloads for power measurement in simulation, emulation, and silicon. Work with verification and software teams to make workloads reproducible and representative of intended use.

• Establish power targets for IP blocks and dies. Produce power rollups across workloads, operating points, and design revisions, including dynamic and leakage power where appropriate.

• Run and interpret RTL and gate-level power analysis. Use switching activity, power reports, and design data to identify major contributors, unexpected activity, and gaps against targets.

• Partner with RTL teams to evaluate changes such as improved clock enables, operand isolation, reduced unnecessary data movement, and more effective low-power states.

• Partner with physical design teams to understand the power impact of synthesis, clock distribution, placement, and implementation choices. Balance proposed savings against timing, area, and performance.

• Build and refine power models and analysis flows so architectural estimates can be compared with implementation results and, when available, measured silicon data.

• Track power optimizations from proposal through implementation and measurement. Quantify the savings achieved and document any performance or functional tradeoffs.

• Communicate power trends, risks, and recommendations to design and architecture teams throughout the silicon development cycle.

• Bachelor’s degree in electrical engineering, computer engineering, or a related field, or equivalent practical experience.

• At least 5 years of relevant experience in ASIC or SoC design, power analysis, low-power design, or silicon power optimization.

• Hands-on experience analyzing power from RTL or gate-level designs and using the results to identify design improvements.

• Working knowledge of Verilog or SystemVerilog, digital design, and the effects of switching activity, clocks, voltage, and leakage on power.

• Experience developing or selecting workloads and activity traces for power estimation, and communicating results to design teams.

• Proficiency with scripting or data analysis, preferably using Python.

• Experience defining and validating clock-gating, power-gating, idle-state, or DVFS features.

• Experience with industry-standard RTL or gate-level power analysis tools and automated power regressions.

• Experience correlating pre-silicon estimates with lab power measurements and investigating differences.

• Familiarity with physical design flows, clock trees, UPF, and power-aware verification.

• Experience optimizing power in large compute SoCs or multi-die designs.