STA/ Physical Implementation (Staff/ Leader)

This role is responsible for driving timing closure and physical implementation quality from pre-layout netlist preparation through post-layout sign-off using Synopsys-based flows. In addition to hands-on technical ownership, this role includes mentoring and training junior and fresher engineers while contributing to critical project milestones.

Responsibilities

Pre-Layout Netlist Preparation & Constraint Engineering

• Develop, review, and maintain high-quality SDC constraints for synthesis and STA using Synopsys Design Compiler / Fusion Compiler
• Perform physical-aware synthesis and early timing optimization using Fusion Compiler
• Prepare DFT-ready pre-layout netlists, including scan stitching constraints and test-mode timing considerations
• Model and validate low-power intent using UPF, including isolation cells, level shifters, and retention strategies
• Identify and resolve pre-layout timing risks related to clock architecture, resets, and mode interactions
• Generate and analyze pre-layout timing reports to guide downstream P&R and STA strategies

Post-Layout STA, Timing Correlation & Sign-off

• Perform full-chip post-layout STA using Synopsys PrimeTime across multi-corner multi-mode (MCMM) environments
• Analyze setup/hold, recovery/removal, clock gating, and asynchronous timing checks
• Perform pre-layout vs. post-layout timing correlation and root-cause analysis
• Drive timing ECO optimization using PrimeTime ECO flows
• Handle advanced physical effects including OCV, AOCV, POCV, SI, and derating methodologies
• Support 2nd-level timing sign-off and tape-out readiness
• Collaborate closely with P&R teams to resolve CTS-, congestion-, and routing-related timing issues

Technical Leadership & Mentorship

• Mentor and train junior and fresher physical implementation engineers
• Review SDCs, STA reports, and ECO strategies generated by junior engineers
• Define and improve STA and physical implementation methodologies, checklists, and sign-off criteria
• Provide technical leadership during timing reviews and design milestones

Qualifications

• B.S. or M.S. in Electrical Engineering or related field
• At least 5 years of hands-on experience in physical implementation and STA
• Strong expertise in Synopsys PrimeTime
• Solid understanding of SDC, UPF, MCMM STA, ECO flows, and physical effects
• Prefer qualification:
• Experience with Fusion Compiler–based implementation flows
• Exposure to advanced process nodes
• Strong debugging and cross-functional communication skills

What we offer:

• Competitive salary + 13th month bonus
• Retention bonus
• Lunch provided, Private Health Insurance, Hybrid work model
• We care about your well-being and personal growth with Fun English classes, Happy Beer Parties, Football & Badminton Club, and more!
• Be part of a cutting-edge R&D center focused on automotive SoCs