UVM Development Engineer

n Hands-on experience in SV/UVM, with experience architecting the TB environment and its various components (driver, scoreboard, monitor, etc.) from scratch. n Hands-on experience with both IP and sub-system/SoC-level verification. n Must have PCIe, DDR and DMA protocol/sub-system verification experience. n Adept at creating the verification plan, creating tests and responsible for 100% code and 100% functional coverage closure (as appropriate IP-level vs. SoC-level). n Adept with the use of simulators/EDA tools like Xcelium, VCS, Verdi, etc. for debugging failures. Need to triage and root-cause failures independently (with minimal supervision). n Excellent communication skills to succinctly discuss issues found with designers/other verification leads and also to close on exceptions/waivers with the appropriate stakeholders. n Good documentation skills. n Prior working knowledge of bug tracking systems like JIRA/Bugzilla in order to capture issues/bugs found.