Verification Engineer Platforms Team

**Please note this role is only open to candidates currently located in and with working rights in the UK**

Location: Preferably based at one of our UK design centres (Bristol or Cambridge).

Seniority: Senior Engineer

Welcome to Codasip

At Codasip, we’re redefining the future of computing. Following a bold strategic pivot toward cyber-resilient semiconductor architectures, we are building next-generation processors and systems where security is embedded at the very core by design, not as an afterthought. As we expand our portfolio of secure, CHERI-enabled technologies and focus on delivering architecture-first security solutions, there has never been a more exciting time to join. We are embarking on clean-sheet designs and expanding the teams of engineers who can establish high-quality working practices as they explore new ground. Be part of a global team shaping the next era of secure computing where innovation, ownership, and impact go hand in hand.

The impact you’ll make

• Verification Strategy & Planning: Define comprehensive verification strategies, plans, test scenarios, and coverage goals from architectural specs, reviewing technical requirements from a verification perspective.
• Testbench & Environment Architecture: Develop and maintain scalable, reusable IP- and system-level verification environments using industry-standard SystemVerilog/UVM, including stimulus generators, checkers, and formal verification setups.
• Execution, Debugging & Closure: Run simulations, perform root-cause failure analysis, support FPGA-based validation, and drive verification closure by resolving coverage gaps and residual risks.
• Quality & Methodology: Develop functional coverage models and SystemVerilog Assertions (SVA) while maintaining automated verification flows to streamline regression and testing pipelines.
• Collaboration & Delivery Tracking: Partner cross-functionally with hardware designers and software engineers, owning estimation, prioritization, and regular reporting on verification metrics, progress, and risks.

What You will bring

• Core Verification Expertise: Solid hands-on experience in IP- and system-level verification using SystemVerilog and UVM, covering constrained-random testing, simulation, and gate-level verification.
• Coverage Closure & Formal Methods: Proven ability to build verification plans, develop functional coverage and assertions (SVA), analyze coverage metrics toward closure, and apply formal verification techniques.
• Programming & Automation: Strong coding skills in languages such as SystemVerilog, Python, C++, or Rust, combined with Linux scripting and workflow automation.
• CI/CD & Development Infrastructure: Familiarity with version control systems (Git, SVN) and continuous integration tools (GitLab, Jenkins) to support automated regression flows.
• Domain Knowledge & Problem Solving: Solid grasp of computer systems and processor architecture, paired with sharp analytical skills to debug complex HW/SW interactions across multidisciplinary teams.
• End-to-End Ownership: Demonstrated ownership of verification deliverables throughout the complete lifecycle—from initial planning through implementation to final sign-off.

Desirable experience

• Knowledge of common system and peripheral protocols, such as AMBA AXI, AHB or APB
• Experience with FPGA-based prototyping or validation

Our UK Design Centers

Our UK design centres in Cambridge and Bristol, established in early 2022, are driving innovation in advanced RISC-V CPU and system development. We are designing high-performance, low-power CPU cores and the associated SOC’s from the ground up to power some of the most demanding applications, from high-performance computing to next-generation embedded systems. This is a unique opportunity to contribute to clean-sheet designs that push technological boundaries and deliver meaningful impact.

We are looking for a Verification Engineer to support the verification of new Codasip IP for use in secure systems. As part of the Platforms team, you will work closely with hardware designers and software engineers on IP verification and the development of system-level testbenches for ASIC implementation and FPGA prototyping.

You will be part of an international team spanning Europe, working with experienced engineers across a range of disciplines to solve challenging problems and explore new ideas. We are looking for someone who combines strong technical ability with initiative, curiosity, and a genuine enthusiasm for innovation within a collaborative engineering environment.

Join us in Cambridge or Bristol and become part of a team redefining what is possible in cyber-resilient semiconductor architectures.

Get to Know Us

Codasip announces strategic pivot and divestiture

CHERI-RISC-V standardisation status - Tariq Kurd | CHERITech'25

Why Codasip went all‑in on CHERI – CHERI Alliance