ASIC Design Engineer

Build the Next Generation of Memory and Storage AI Infrastructure Technology

We are an established and growing semiconductor company specializing in advanced storage solutions, SSD controllers, and high-performance SoC technologies supporting AI & other cutting-edge markets. Our products power data-intensive applications around the world, and we're looking for talented engineers to help shape the future of memory and storage innovation.

This opportunity is ideal for engineers with experience in NAND Flash, SSD controllers, DRAM, memory controllers, storage ASICs, or related semiconductor technologies who are passionate about digital design, SoC architecture, and RTL development.

As part of our global engineering organization, you'll collaborate closely with teams across the United States, China, and Taiwan while contributing to complex, production-proven silicon designs

What You'll Be Doing

• Shape the microarchitecture of next-generation SSD controllers and storage subsystems optimized for AI workloads, from concept through tape-out.
• Author detailed design specifications, microarchitecture documents, and implementation guidelines that become the team's source of truth.
• Design and implement key functional blocks in Verilog/SystemVerilog RTL, owning quality and timing from first draft to sign-off.
• Partner with the verification team to define test plans, drive coverage closure, and debug full-chip simulation and silicon bring-up.
• Collaborate with physical design to deliver clean RTL-to-GDS hand-offs, meeting PPA targets on schedule.
• Work alongside firmware and system teams to align feature implementation with product-level performance goals.
• Drive continuous design analysis to improve power, performance, and area (PPA) across the chip.
  

What We're Looking For

Required Qualifications

• Bachelor's degree or higher in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 3+ years of hands-on ASIC digital design experience, with strong RTL development skills in Verilog or SystemVerilog.
• Solid understanding of the full ASIC design flow - front-end through back-end (synthesis, STA, CDC, lint).
• Experience supporting post-silicon bring-up and lab validation.
• Proficiency in at least one scripting language (Python, Tcl, Perl, or Shell).

Language Requirements

• Fluent in Mandarin Chinese and English
• Ability to collaborate with engineering teams in China and Taiwan

Preferred Qualifications

• Background in SSD controller, Flash Memory or storage system ASIC design.
• Familiarity with AI/ML workload acceleration, memory/storage hierarchy, or high-throughput data path design.
• Hands-on experience with Design Compiler, formal verification, or CDC signoff flows.
• Knowledge of UVM-based verification methodology.
• Experience with companies in the memory, storage, or semiconductor industries is desirable.

Benefits

• Medical, Dental, Vision
• Competitive pay ($140k-$190k dependent on experience)
• Future equity opportunity
• PTO
• 401k
• Some relocation assistance avail