DDR Design Engineer
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- Spain
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- Visa sponsorship
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Are you passionate about microprocessor architecture? We need you! As a Senior Memory Design Engineer, you play a crucial role in designing and developing memory subsystem solutions for our semiconductor portfolio. You will work within the Memory Design Team and work closely with other teams’ highly skilled engineers to create efficient and high-performance memory subsystems that are essential for modern designs.
Requirements
Industrial experience +8 years
Knowledge of DDR or HBM memories. Proven experience in design and/or integration of memory controllers.
Experience in AXI protocol.
Proficiency in RTL design using Verilog or VHDL
Experience with Timing and Timings Constraints
Experience with basic block level testing
Desired
Master or PhD
Knowledge of scripting languages (Python, Perl, Bash, TCL).
Knowledge of revision control methodology and tools (git, svn).
Knowledge of coherency concepts and protocols.
Experience in memory map definition.
Why Semidynamics?
Work at one of Europe's most promising deep-tech semiconductor scale-ups.
Accelerated development path.
4 days per week in the Barcelona office (city center), 1 WFH.
1 week of work from everywhere in the world.
Competitive package.
A collaborative, technical, and growth-oriented environment that values direct ownership and clear thinking.