EDA R&D Engineer (C++, AI for Physical Design)

EDA R&D Engineer (C++, AI for Physical Design)

This is not a conventional Physical Design Engineer role. If your experience is primarily running P&R flows, even expertly and at advanced nodes, this probably isn't the one.

We're working with an early-stage semiconductor software company building AI-native optimization technology for backend chip implementation. The technology works alongside existing commercial EDA flows and tackles PPA optimization directly.

They're building a small founding engineering team with significant technical ownership and multiple positions open.

The strongest candidates demonstrate at least two of three areas:

EDA tool development

You've written production software inside EDA/CAD technology — placement, routing, timing, synthesis, DRC/physical verification, optimization algorithms or design-space exploration. We're looking for C/C++ development of the underlying technology, rather than simply scripts or flows around commercial tools.

Applied AI/ML

You've built or deployed models, agents, reinforcement learning or other ML/AI techniques against real engineering problems.

Exceptional physical design depth

You understand placement, routing, congestion, timing closure, PPA and/or physical verification deeply enough to understand why implementation tools behave the way they do — not simply how to operate them.

Two of the three is enough. Nobody is expected to have all three.

Backgrounds that fit

We're particularly interested in engineers from EDA vendor R&D teams, internal CAD/tool-development groups, semiconductor R&D organizations, university CAD research and technically ambitious startups.

Experience at an EDA vendor alone isn't enough. Application engineering, flow development and commercial-tool usage are different from developing the underlying EDA technology.

Startup experience is a plus, as is evidence that you've built something from scratch.

Seniority

We're deliberately flexible. Around 2–3 years of relevant industry experience is a useful starting point, but exceptional graduate researchers and engineers earlier in their careers are genuinely in scope. Experienced Senior/Staff engineers who remain deeply technical are equally relevant.

There is no specific PhD requirement. Technical profile matters more than years or academic pedigree.

Location: Bay Area Peninsula, approximately four days onsite

Compensation: $250,000–$350,000 base + meaningful early-stage equity

Visa sponsorship: Available

Relocation support: Available

Hiring: Multiple positions

If you've spent your career wanting to build the tools rather than simply use them, particularly where EDA, optimization, physical design and AI intersect, we'd like to hear from you.