Physical Design Engineer

About Etched Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep chain-of-thought reasoning. Physical Design Engineer Etched is looking for exceptional PD engineers to join our team. The candidate will be responsible for working with 3rd party design services to implement and verify physical designs, and will help Etched as we work to improve iteration speed on physical design. Representative projects: Supervise the outsourcing of physical design to a 3rd party service Deeply understand what is involved in physical design Running Physical Design flows to close blocks, support ASIC infrastructure, automate Physical Design flows, improve CAD infrastructure Drive dashboards that show the convergence of projects related to Physical Design Optimize tool flows, working with EDA vendors to incorporate the latest features Accountable for block level closure Requirements: 2+ years of previous experience with PD Tools, flow, and design methodology from RTL synthesis to GDSII sign-off Experience with back-end design and timing closure on 3nm-7nm Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis Deeply creative and able to think from first principles Desired qualifications: Familiarity with transformer models and machine learning. Familiarity with OpenROAD and other automated RTL-to-GDSII flows ​Ability to program with Python or another scripting language. We encourage you to apply even if you do not believe you meet every single qualification. How we’re different: Etched believes in the Bitter Lesson . We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs. We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed. Benefits: Full medical, dental, and vision packages, with 100% of premium covered, 90% for dependents Housing subsidy of $2,000/month for those living within walking distance of the office Daily lunch and dinner in our office Relocation support for those moving to Cupertino