Physical Design Engineer - Flow & Methodologies

About Etched Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference . Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary Etched is building a new category of AI hardware: frontier inference clusters. As a Physical Design Methodology Engineer, you will architect our PD flow from first principles. You will own the infrastructure that allows our design team to iterate at unprecedented speeds, directly accelerating our time-to-market and enabling PPA gains that aren't possible with off-the-shelf CAD methodologies. Key Responsibilities Architect, build, and maintain our automated RTL-to-GDSII flow, from synthesis through place and route to signoff handoff. Automate PD flows end to end, including regression running, run management, and release and version control of flow configurations. Build and own the CAD infrastructure supporting PD, including tool version qualification and deployment, and efficient use of compute and licenses. Drive dashboards that show the convergence of projects related to PD, including timing, physical verification, and utilization trends. Optimize tool flows and work with EDA vendors to evaluate and incorporate the latest features. Define reference flows, QoR targets, and delivery checklists for 3rd party physical design services, and audit deliveries against them. Partner with block and top-level owners to debug flow issues and encode fixes into the methodology rather than one-off patches. Create block level and full chip level PG mesh from scratch using design rule documents, design requirements, and EM/IR feedback. Create and maintain a DRC-clean floorplanning flow and enable floorplan signoff checks. Drive PPA tuning to optimize tool settings for best power, performance, and area outcomes. Establish and maintain timing correlation from pre-route through post-route and between implementation and signoff tools. You may be a good fit if you have 5-10+ years of previous experience with PD or PD methodology/CAD Experience building and owning automated RTL-to-GDSII flows used by multiple block owners Experience creating block level and full chip level PG mesh from scratch, including interpretation of design rule documents and EM/IR analysis Experience with DRC-clean floorplanning flows and automated checks Experience with Cadence (Innovus, Genus) or Synopsys ( Fusion Compiler) automated RTL-to-GDSII flows Experience with PPA tuning and timing correlation across pre-route, post-route, and signoff environments Experience integrating sign-off tools (PrimeTime, Tempus, Voltus, Pegasus, Calibre) into production flows Experience with back-end design on advanced process nodes (5nm and below) Experience with UPF-based low power design methodology and multi-mode multi-corner setup Strong Tcl and Python skills for flow development and automation Deeply creative and able to think from first principles Strong candidates may also have experience with Familiarity with modern ML and LLM model architectures Familiarity with AI tools for programming/coding Experience with compute farm and job scheduler optimization for EDA workloads Startup experience or comfort working in fast-paced environments Benefits Medical, dental, and vision packages with generous premium coverage $500 per month credit for waiving medical benefits Housing subsidy of $2k per month for those living within walking distance of the office Relocation support for those moving to San Jose (Santana Row) Various wellness benefits covering fitness, mental health, and more Daily lunch and dinner in our office Unlimited compute budget subject to ROI justification How we’re different Etched believes in the Bitter Lesson . We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors. We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.