Senior E/E & Semiconductor Engineer - ASIC Emulation Engineer

Company Overview The client company is a dynamic and innovative technology company that specializes in providing cutting-edge solutions. They are currently seeking a highly skilled Emulation Engineer to join our team and contribute to our partnership with CapGemini, as a consultancy partner at Meta. This role is a full-time position and is critical to their ongoing success in delivering exceptional service to our clients. Job Title Emulation Engineer Job Location Sunnyvale, CA or Austin, TX Years of Experience 5-8 years of relevant experience Required Skills Candidates must have a minimum of 4 years of experience specifically in Emulation engineering and be proficient as an Emulation ASIC Engineer. Job Status Full Time HIRE ONLY - no Corp to Corp applicants or profiles. Candidate Requirements US citizens, Permanent Residents, Green Card holders, and H4 visa holders are welcome to apply. We are unable to accommodate H1B Transfers at this time. Relocation Candidates from across the nation are encouraged to apply as we offer relocation assistance for the right candidate. Compensation The salary for this position can go up to $190,000 for an excellent candidate. Minimum Qualifications 5+ Years of experience with EDA tools and scripting languages used to build tools and flows for complex emulation environments. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Experience with current emulation technologies and methods, such as simulation acceleration, in-circuit emulation, speed bridges, virtual prototyping, and hybrid methods. Preferred Qualifications Proven track record of ‘first-pass success’ in ASIC where emulation is one of the key validation tools. Understanding of compilation and build flow with experience building images from scratch with necessary design modifications to adapt to emulation. Experience with verification, SoCs or similar designs. Experience in architecting emulation systems for various design scales (IP blocks, SOC, multi-chip system) with an understanding of trade-offs between performance and ease of debug. Experience managing multiple design releases and working with cross functional teams to support and debug customer issues. Experience with SystemVerilog and C++ to model RTL components and transactors. Experience with post-silicon bring up, debug and reproducing issues on emulator. Experience with Palladium & Protium tools. Experience with Python and TCL scripting languages. Experience interfacing with the design, verification, validation and software development teams and understand their needs from an emulation perspective.