Staff Mixed-Signal Digital Design Engineer

Staff Mixed-Signal Digital Design Engineer - Cork - (Relocation offered for EU-based Candidates)

We're looking for an experienced digital design engineer to help develop the next generation of high-performance, low-power mixed-signal IP for advanced semiconductor products.

This is an opportunity to join a specialist engineering team working across architecture, ASIC design, digital signal processing and hardware implementation. You'll play a key role in taking digital designs from microarchitecture definition through RTL implementation, validation and physical implementation, collaborating with engineers across multiple disciplines.

What you'll be doing

• Architect, design and implement digital components of mixed-signal IP, including SerDes, DDR PHY, PLL/DLL/FLL, ADC/DAC and sensor-related designs.
• Define microarchitectures and develop high-quality RTL for complex ASIC designs.
• Apply digital design, computer architecture and signal-processing techniques to optimise power, performance and area (PPA).
• Use front-end ASIC design tools and flows, including lint, clock-domain crossing (CDC), design-for-test (DFT), synthesis, formal verification and static timing analysis (STA).
• Work closely with design verification engineers to define test plans, validate functionality and resolve design issues.
• Collaborate with physical design engineers to support implementation and achieve design targets.
• Produce design specifications and technical documentation.
• Support silicon bring-up, testing and debugging alongside the wider engineering team.

Required Experience

• A degree in Electrical Engineering, Computer Engineering or a related technical discipline.
• At least 5 years of relevant ASIC digital design experience, including microarchitecture definition and RTL development.
• Strong practical experience with Verilog and/or SystemVerilog.
• Experience with front-end ASIC tools such as Design Compiler, Fusion Compiler, ModelSim, VCS, SpyGlass and PrimeTime.
• An understanding of ASIC design flows and the interaction between RTL design, verification and physical implementation.
• Strong communication skills and the ability to collaborate effectively within a technically demanding engineering team.

Desired Experience

• Low-power digital design and PPA optimisation.
• Computer architecture, DSP or algorithm development.
• Scripting with Python or Perl.
• Hands-on experience designing at least one mixed-signal IP domain, such as:
• SerDes and high-speed interfaces, including USB, PCIe, MIPI or UFS.
• DDR PHY and memory interfaces.
• Timing circuits, including PLL, DLL and FLL.
• Data converters, including ADC and DAC.
• Digital components of sensor interfaces.