Formal Verification Lead

Specialization: Equivalence Checking and Low Power Verification

Job Description

Our partner is looking for an experienced Formal Verification Lead to ensure functional equivalence and correct power behavior across complex semiconductor designs.

The role focuses on Logic Equivalence Checking (LEC), UPF verification, debugging and signoff, working closely with RTL, synthesis and physical design teams.

Location: Barcelona, Spain
Working model: Hybrid
Employment: Full time

Responsibilities

• Perform RTL to Gate and Gate to Gate equivalence checking.

• Verify power intent using UPF and investigate functional mismatches.

• Debug issues involving clock gating, retention, isolation and level shifters.

• Ensure equivalence closure across synthesis, physical implementation and ECO stages.

• Develop automation scripts and improve verification methodologies.

• Collaborate with RTL, DFT, synthesis and physical design engineers.

Mandatory Requirements

• 7+ years of experience in Formal Verification or LEC.

• Strong experience with Synopsys Formality and/or VC LP.

• Practical knowledge of UPF and low power design.

• Experience with RTL, gate level netlists, synthesis and equivalence debugging.

• Experience with hierarchical LEC flows and signoff.

• Scripting skills in TCL, Python or Perl.

• Bachelor's or Master's degree in Electronics, Electrical Engineering or related field.

Optional / Desired

• DFT and scan insertion knowledge.

• STA and physical design experience.

• ECO verification and methodology automation.

What's in it for you?

• Flexible working hours

• Hybrid model, 4 days office, 1 day from home

• 1 week per year working from anywhere

• 25 days annual leave plus December 24 and 31

• Monthly food allowance

• Private medical insurance

• Relocation bonus

• Housing search support

• Visa support, subject to approval

• Family relocation support, subject to eligibility

• Virtual shares, subject to plan terms

• Language classes

• Tax incentive