FPGA Engineer

FPGA Engineer

About Astrape Networks

Astrape Networks is rebuilding the nervous system of the AI data center. Today's AI clusters run three or four parallel networks because no single fabric is fast or flexible enough. We collapse them into one adaptive fabric that fuses optical and electronic switching and decides, flow by flow and at microsecond speed, how data should travel. The result is up to 60% less energy, 50% more traffic, and a network that scales to millions of GPUs.

Role Overview

As Senior FPGA Engineer, you'll build the silicon logic at the heart of our networking system, from SmartNICs to hybrid optical switches. You'll own your designs end to end: you architect them in VHDL or Verilog, prove them in simulation, close timing, and watch them come alive on real hardware. When the full system runs under load, you'll be in the lab with our software and networking engineers, hunting down the last bottleneck and making the whole thing fly.

You'll join a dedicated FPGA team of experienced senior engineers who know exactly what it takes to push logic to its limits. You'll review each other's designs, bounce ideas around and tackle the toughest technical challenges together. Together with our system architects, you'll decide which features go into hardware, and bring them to life.

What you'll do

• Design and optimize high-performance FPGA logic in VHDL and/or Verilog for SmartNICs and hybrid optical switches
• Verify your designs by writing test cases and scenarios in our Python-based simulation environment
• Integrate your own designs and third-party IP cores into our FPGA projects
• Run timing analysis and drive designs to timing closure
• Validate on target and debug directly on hardware
• Take part in system-level performance testing and debugging together with the software and networking teams

Requirements

• Master's degree in electronics engineering, or equivalent experience
• Strong hands-on experience with VHDL and Verilog development
• Programming skills in Tcl and Python
• Proven experience in timing analysis and timing closure
• Experience with unit simulation testing and test automation (e.g. Jenkins)
• Comfortable working in a Linux environment
• Solid understanding of networking concepts: Ethernet, TCP/IP, MAC addressing, buffering
• Strong hardware debugging skills, from simulation waveforms to on-target issues
• Familiarity with Xilinx FPGA tools and QuestaSim/ModelSim is a plus
• Experience with the Cocotb verification environment is a plus
• Knowledge of high-speed interfaces such as DDR4, Ethernet, PCIe, AXI4 and AXI-Lite is a plus

Where you'll work

Based in Schelle, Belgium, in a hybrid setup with two days a week on-site. You must have the legal right to work in Belgium at the time of application. We can't offer visa sponsorship or work permit support.

Talent and drive are the only prerequisites. The rest compiles over time.