FPGA Validation Design Engineer

FPGA Validation Design Engineer

Contract Duration: 3 months (with extensions)

Location: Leuven (Belgium)

Start Date: ASAP

Working Arrangement: Hybrid – 3 days onsite and 2 days remote (some flexibility may be available following induction).

Experience: 5+ years of relevant semiconductor / FPGA engineering experience.

Role Overview

We are looking for an experienced FPGA Validation Design Engineer with a strong background in ASIC design verification, RTL and FPGA implementation.

The successful candidate will be responsible for adapting existing ASIC RTL designs so they can be integrated and implemented on an FPGA platform. They will manage the FPGA implementation flow, carry out synthesis and place and route, verify the FPGA design database, and ensure timing requirements are achieved.

This is a hands-on engineering position requiring someone who understands both ASIC and FPGA environments and has practical experience debugging and validating designs on physical FPGA hardware.

Key Responsibilities

• Modify and adapt existing ASIC RTL designs to enable integration and implementation within an FPGA.
• Set up, configure and manage the FPGA development and implementation flow.
• Perform FPGA database verification to ensure the design is ready for implementation.
• Carry out FPGA synthesis, place and route.
• Analyse timing reports, identify timing violations and achieve timing closure.
• Update and optimise timing constraints to meet required performance targets.
• Load FPGA bitstreams onto physical FPGA development boards.
• Debug and troubleshoot FPGA hardware issues.
• Perform design verification and functional validation of complete devices and CPU-related designs.
• Identify, investigate and resolve design and implementation issues.
• Work closely with design and verification teams to ensure the successful implementation and validation of the FPGA design.

Candidates must have:

• 5+ years' experience in FPGA, ASIC or semiconductor design engineering.
• Strong experience in digital design verification.
• Practical experience with FPGA design, validation and implementation.
• Strong knowledge of SystemVerilog.
• Experience using UVM (Universal Verification Methodology).
• Experience verifying complete devices and CPU/processor designs.
• Strong understanding of ASIC RTL design and FPGA integration.
• Hands-on experience with FPGA synthesis, place and route.
• Experience with timing analysis, timing constraints and timing closure.
• Experience debugging and validating designs on physical FPGA boards.
• Ability to work independently and deliver within a project-based environment.

Ideal Candidate Profile

We are particularly interested in engineers who have worked across both ASIC Design Verification and FPGA Implementation.

The ideal candidate will not simply have simulation or verification experience. They must also understand how to take an existing ASIC RTL design, modify it for FPGA integration, run the FPGA implementation process and debug the resulting design on physical hardware.