FPGA Validation Design Engineer

Job Description

We are looking for an experienced FPGA Validation Design Engineer to support ASIC-to-FPGA integration and design verification. The role focuses on RTL modification, FPGA implementation, timing closure, and hardware debugging.

Key Responsibilities

• Adapt and modify ASIC RTL for FPGA integration.
• Set up and execute FPGA development and verification flows.
• Perform FPGA database verification, synthesis, and place-and-route.
• Analyse timing reports, update constraints, and achieve timing closure.
• Debug FPGA bitstreams on hardware boards.
• Perform device- and CPU-level design verification.

Required Skills

• 5+ years of relevant semiconductor, FPGA, or design verification experience.
• Strong knowledge of SystemVerilog and UVM.
• Experience in device-level and CPU verification.
• Hands-on experience with RTL, FPGA implementation, timing analysis, and hardware debugging.
• Fluent English.

Start Date: ASAP

Project Duration: 3 months

Working Arrangement: Hybrid – 3 days onsite, 2 days remote (flexibility possible after induction)

Language: Fluent English

Experience: 5+ years