[Japan] Accelerator IP Design Engineer (ASIC, RTL)

Introduction Edgecortix Inc. is seeking a Hardware Design Engineer with proven RTL/logic and ASIC design expertise. If you have a strong desire to build state-of-the-art digital chips and systems join us and let's reshape the future of AI. About Edgecortix At Edgecortix we are a deep-tech startup revolutionizing edge computing with artificial intelligence and novel high efficiency silicon on chip design. Originating from multiple years of research, our unique AI hardware & software co-design principle and the Dynamic Neural Accelerator ® AI processor IP are geared towards positively disrupting the rapidly growing artificial intelligence edge hardware space and bring the power of AI and machine learning to all kinds of devices. Our operations are headquartered in Tokyo, Japan, with offices in Singapore, Virginia, California in the US. In addition, we are starting a new Design Center in India, located in Hyderabad. The Team As an engineering driven company we are working to define and solve the hardest problems in AI including computer vision, speech, and natural language, geared towards real-time capabilities on small to medium form factor devices. We originated out of multiple years of research, as such at our core we value learning, intellectual curiosity, and self-starters. We have the ambitious goal of enabling cloud-level performance with significantly better energy-efficiency for AI inference at the edge. Your Role and Responsibilities: Ideal candidates will have expertise in several of the following areas: RTL Design and module-level verification of modules for Edgecortix inference accelerator IP. Participate in synthesis, STA, and power estimation activities. Propose and implement low-level micro-architectural optimizations for better area, power, and placeability/routability of design targeting specific tech processes, power, and area budgets. Work closely with our architects to support architectural-level decisions providing expert feedback to ensure high design scalability. Collaborate with our architects and compiler engineers to determine the best way of implementing new functionality and defining architectural specs. Engage in system integration activities for SoC design using third-party IPs and integration tools. Engage in IP-level and system-level verification and debugging activities using SystemVerilog and UVM. Embrace high standards of engineering practices such as code reviews, technical documentation, propper testing process, continuous integration, and release engineering. Desired Qualifications (ASIC) Ability to write clean, readable, synthesizable RTL. Familiarity with AXI, Avalon or similar protocol. Experience in low power RTL design. Experience in performing logic synthesis using Cadence or Synopsys tools. Experience in writing timing constraints and power intent definitions. Experience in optimizing design for timing. Experience in using power analysis tools such as Joules or PowerPro. Understanding of Physical Design issues. Understanding of using fixed-point arithmetic for approximating floating-point computations. Experience with verification using SystemVerilog and UVM. Experience with DDR, PCI-E, MIPI CSI or other high speed protocols is a plus. Decent scripting and automation skills using TCL, Python, and Make. Basic programming skills in statically typed languages such as C++ or Java. What’s in it for you? Make a difference : you will have the opportunity to join a well-funded fabless AI semiconductor startup that is disrupting the AI software and hardware co-design space. Be an integral part of its growth and momentum. Benefits and Perks · Highly competitive salary and stock options · Flex work time and ability to work fully remotely · Support for obtaining visa and relocation support (in case of non-remote)