Senior Design Verification Engineer (Contract / Remote – Romania & EU)

Location: 100% Remote (Based in Romania or European Union)

Engagement Type: B2B Contract (6–12 months, renewable)

Overview

We are seeking a Design Verification Engineer with 3 to 8 years of experience to join our silicon verification team. In this role, you will develop UVM-based testbenches, write comprehensive test plans, and drive functional coverage closure for complex digital IPs and SoCs.

Key Responsibilities

• Develop and maintain modular, scalable testbenches using SystemVerilog and UVM.
• Define verification architectures and write detailed verification test plans from RTL specs.
• Implement constrained-random tests, assertions (SVA), and functional coverage models.
• Debug RTL, testbench failures, and protocol violations down to the waveform level.
• Track and drive code coverage and functional coverage toward full tape-out closure.

Required Qualifications

• 3–8 years of hands-on digital IC/ASIC verification experience.
• Strong proficiency in SystemVerilog and UVM.
• Proven track record with constrained-random verification, assertions (SVA), and coverage-driven closure.
• Solid experience with standard industry simulators (e.g., Synopsys VCS, Cadence Xcelium, or Siemens Questa).
• Familiarity with scripting languages (Python, Perl, or Bash) for regression automation.
• Professional working proficiency in English.
• Legally able to work as an independent contractor (B2B / PFA / SRL) within Romania or an EU member state.

Preferred Qualifications

• Experience with standard interfaces and protocols (e.g., PCIe, AXI/AHB, Ethernet, DDR, or USB).
• Familiarity with formal verification techniques or low-power verification (UPF/CPF).
• Prior experience collaborating across distributed, multi-timezone engineering teams.